Synopsys, Inc. (Nasdaq:  SNPS) today announced that its IC Validator physical verification product has been successfully used for signoff on more than 100 tapeouts at advanced FinFET nodes. These tapeouts were completed with process technologies from multiple foundries at 16nm, 14nm, 10nm and 7nm. IC Validator’s massively parallel scalability to more than 200 CPUs has proven a critical factor in its ability to deliver overnight run times for today’s highly complex technology rules and very large designs. Synopsys has cooperated closely with foundries for several years to ensure the uncompromising accuracy of IC Validator’s results. This dependable accuracy has been key to IC Validator’s growing list of successful adoptions by industry leaders in many markets ranging from top CPU and GPU design companies in the US to leading fabless SoC designers in Taiwan and Japan.

IC Validator, part of the Synopsys Galaxy Design Platform, is a comprehensive and highly scalable physical verification tool suite including DRC, LVS, programmable electrical rule checks (ERC), dummy fill and DFM enhancement. IC Validator is configured to meet the challenges of today’s extremely large designs by enabling 8 CPUs with a single license. It uses both multi-threading and distributed processing over multiple machines to provide scalability benefits that extend to more than 200 CPUs. IC Validator enables coding at higher levels of abstraction and is architected for near-linear scalability that maximizes utilization of mainstream hardware, using smart memory-aware load scheduling and balancing technologies.

IC Validator is a companion product to the IC Compiler II place-and-route system for In-Design physical verification. In-Design is enabled by the intelligent integration of IC Validator and IC Compiler II place-and-route, making it possible for engineers to perform independent signoff-quality analysis earlier, before the design is finalized and while correction can be automated. In-Design technology also enables new high-productivity functionality within the place-and-route environment, including automatic DRC repair, improved quality of timing results with timing-aware metal fill, and rapid ECO validation. In-Design physical verification eliminates expensive iterations with downstream analysis tools and maintains a convergent design flow to physical signoff.

“As manufacturing complexity is placing increased challenges on designers to deliver within schedule, it is extremely important that we continue to collaborate closely with leading foundries to deliver high-performance solutions,” said Bijan Kiani, vice president, product marketing, Design Group at Synopsys. “This milestone confirms our mature ecosystem strategy that has led to strong growth in IC Validator’s market share.”