In-line metrology for characterization and control of extreme wafer thinning of bonded wafers

In-line metrology methods used during extreme wafer thinning process pathfinding and development are introduced.

BY M. LIEBENS, A. JOURDAIN, J. DE VOS, T. VANDEWEYER, A. MILLER, E. BEYNE, imec, Leuven, Belgium & S. LI, G. BAST, M. STOERRING, S. HIEBERT, A. CROSS, KLA-Tencor Corporation, Milpitas, California

The pace of innovation in device packaging techniques has never been faster or more interesting as at the present time. Previously, data were sent through wires where in recent packages, components are connected directly using different 3D interconnect technologies. As the 3D interconnect density is increasing exponentially, pitches need to reduce to 5μm and below. Current interconnect technologies of 3D-SIC (3D-Stacked IC) do not offer such high densities. Parallel front-end of line wafer processing in combination with wafer-to-wafer (W2W) bonding and extreme wafer thinning steps in the 3D-SOC (3D System On Chip) integration technology schemes, as depicted in FIGURE 1, enable the increase of 3D interconnect density.

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During the extreme wafer thinning process pathfinding and development, different thinning techniques like grinding, polishing and etching were evaluated in [1] and [2] to target a final Si thickness specification of 5μm. For the comparison of the thinning techniques, multiple success criteria were defined to which the thinning process must initially comply. Firstly, the final Si thickness (FST) across the wafer needs to be within certain limits to achieve, for example, a stable via-last etch process with requirements to land on correct metal layers. Secondly, the thinning process may not induce damage on the top Si across the wafer and especially at the wafer edge which would directly impact the physical yield of the complete wafer stack. Finally, the wafer surface nanotopography (NT), shape and flatness need to be in control to ensure proper subsequent W2W bonding when going to multi- wafer stacks beyond N=2. To allow us to achieve these challenging criteria the metrology systems used must cope with areas of the wafer previously deemed to be in the “minimal care zone” of 1 – 2mm from the wafer edge. The wafer edge characterization must also go hand in hand with patterned wafer topography after thinning to maximize physical wafer yield.

In this paper, the in-line metrology methods used during the extreme wafer thinning process pathfinding and development are introduced. These metrology tools supplied results that enabled us to determine where the extreme wafer thinning process can be improved. The same techniques can eventually be used to validate the improvements and to monitor process stability when processes are released for volume production.

Metrology methods

Wafer Level Interferometry. For FST measurement and wafer surface shape and NT, a patterned wafer geometry system (KLA-Tencor’s WaferSightTM PWG) was used. This is a dual Fizeau interferometry system and simultaneously measures both the front surface and back surface height of patterned wafers at high spatial resolution. During the measurement, the wafer is supported in a vertical position to reduce any wafer distortion. The whole wafer acquisition is completed in a single shot allowing measurement of the front and back surface topography as well as wafer flatness and edge roll-off.

This tool is specifically designed for wafer geometry measurements with 1nm measurement precision and has previously been used to qualify the impact of wafer geometry on CMP in [3] and [4] and to determine the NT of a full wafer post CMP [5]. Using the device layout, the full-wafer NT map can be divided into individual dies and the range or peak-valley (PV) value can be the output for each individual die.

For this paper, the patterned wafer geometry (PWG) system is used to measure wafer thickness at multiple steps during W2W bonding and extreme wafer thinning to derive the final Si thickness of the top wafer after thinning. The thickness results as supplied by PWG is the relative height variation measured by interfer- ometry, with respect to the local absolute wafer thickness measured by a capacitive sensor before the interferometry measurement is performed. The tool can supply 2D and 3D representations of the wafer thickness measurement at high spatial resolution as depicted in FIGURE 2.

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Wafer Edge Inspection and Metrology. The all-surface wafer inspection and metrology system utilized (KLA-Tencor’s CIRCL-APTM) contains an edge inspection module. This module uses: (1) a laser scanning setup revolving around the wafer bevel; and, (2) a lateral edge profile camera acquiring images of the wafer edge while the wafer is rotating. The laser scan comprises the laser, multi-channel optics and photodetectors/photomultiplier tube (PMT).

The lateral edge profile images are used to measure and quantify the edge shape and edge trim dimensions (see FIGURE 3). Based on the edge shape, an optimal trajectory of the revolving optics is calculated for profile-corrected inspection to ensure proper incident of light on the wafer sample and to obtain good signal-to-noise ratio.

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The revolving laser scanner is used to perform simulta- neous edge inspection and metrology using brightfield, darkfield and phase-contrast modes to capture a broad range of wafer edge defect types with sensitivity down to 0.5μm. Images are acquired in the different contrast modes from all zones comprising the wafer edge, i.e. top and bottom near-edge (5mm), top and bottom bevel, and apex. Part of a full wafer edge inspection image, including notch, is shown in FIGURE 4.

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Inspection is performed basically by comparing neigh- boring pixels on a tangential line. Pixels with a contrast or gray value difference exceeding a certain user-defined threshold are considered to be part of defects. Using rule-based binning techniques and by defining regions of interest and care areas, a high defect classification accuracy and purity of the defects of interest can be achieved by the implemented defect classification strategy.

Metrology is performed by detecting edge transitions on radial lines enabling characterization of coverage, concentricity and uniformity of layers, films or other line features on the wafer edge.
Front Side Metrospection. The all-surface wafer inspection and metrology system also contains a front side inspection module that uses: (1) time-delay-integration (TDI) technology with concurrent brightfield (BF) and darkfield (DF) inspection channels; (2) bright LED illumination for precision and stability; and, (3) a set of recipe-selectable objectives to give different lateral resolutions.

The TDI camera detects an interference signal from the top and bottom surfaces of thinned Si. An example of such fringes is shown in FIGURE 5. The front side inspection module uses three illumination colors (RGB) that give three sets of interference signals, each has its own characteristic amplitude and frequency. By analyzing these signals, the Si thickness at the edge of the thinned wafer can be determined. The high resolution optics of the front side inspection module enables accurate thickness measurement when the edge rolls off rapidly.

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Edge Defectivity. Using edge defect inspection and classification, it was possible to compare different wafer thinning process sequences with respect to grinding-induced damage, edge chipping and delamination, and to fine-tune the process by minimizing the defect count of these defects of interest.

FIGURE 6 is showing the results from automated edge defect inspection of wafers which received two different thinning process sequences. By placing inspection care areas on the regions of interest, i.e. near the wafer edge of the top thinned wafer, and by specifying defect classification rules, the inspection detected edge chippings and classified them accordingly with high accuracy. The defect count of detected edge chippings on the wafer thinned by approach A was significantly higher than on the wafer thinned by approach B. The edge integrity was better maintained when wafers are thinned using approach B. The details of the process sequences can be found in [1].

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When further exploring thinning approach B, a detailed edge inspection showed that the thinning process sequence induced a lateral shrinkage of the top wafer besides the normal wafer thinning, resulting in pattern exposure from the landing wafer as can be seen on the right inspection image of Fig. 6.

Global Wafer Thickness. The most important element in the extreme wafer thinning process is a precise control of the FST, and its variation, with a maximum 3σ repeatability of 50nm to obtain a precision-to-tolerance ratio smaller than or equal to 0.1. The FST was measured by PWG and is the subtraction of the thickness measurement of the bottom wafer from the thickness measurement of the wafer stack after bonding and thinning, according to below equation.

The different components of this equation are depicted in FIGURE 7. Thickness #2(x,y) is the thickness of the total stack after W2W bonding and thinning. Thickness #1(x,y) is the thickness of the bottom wafer. Finally, to know the FST of the top wafer, the thickness of the dielectrics on top and bottom wafer are subtracted. The latter thickness is considered to be constant since the variation of the dielectric thickness is negligible compared to the variation of FST.

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FIGURE 8 shows the thickness profile of the top Si layer after the thinning process sequence as measured by PWG. The FST varied about 2μm center-to-edge, with a strong gradient when approaching the wafer edge. Between wafer edge and 2mm from the wafer edge, it becomes challenging for standard wafer metrology tools to measure the thickness profile. Reasons are the wafer edge exclusion imposed by the tool and the non-opaque behavior of Si at a certain thickness in function of the wavelength applied by the metrology tool. The CIRCL-AP was used to investigate the edge profile of the top wafer to complete the full wafer charac- terization of the FST. Result details are elaborated in the following sections.

The results of the PWG measurements showed a clear correlation with standard ellipsometry-based metrology measurements, as can be seen in FIGURE 9. The advantage of PWG over ellipsometry is that more points on the wafer are measured at higher throughput and results are more reliable with the presence of patterns in the complex stack of 3D-SOC W2W bonded wafers.

Edge Metrology. For the wafer edge profile of the bonded wafer pair after thinning, it is expected to see a stepwise decrease of the FST of the top wafer due to the edge trim of the top wafer before bonding (FIGURE 10). However, the FST showed a slower decrease when approaching the wafer edge.

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With the edge metrology function, CIRCL-AP was capable to detect and report from what radius the final Si thickness starts to decrease, as depicted in FIGURE 11. It is expected to see a uniform area of the top wafer top surface that extends to a radius of about 149.5mm, in case the top wafer received an edge trim width of 0.5mm. However, from radius 147.5mm, the FST started already to decrease towards the wafer edge. This decrease is the lateral shrinkage that was mentioned previously when discussing the results presented in Fig. 6.

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Edge Thickness. The lateral shrinkage was further confirmed by detailed thickness measurements focusing on the wafer edge using the CIRCL-AP’s front side inspection module. The inspection tool with metrology capabilities (metrospection) showed the thickness profile and quantified the decrease as a function of wafer radius R and angle θ as depicted in FIGURE 12. There is a gradual thickness decrease noticed from 3μm to 0μm indicating that there is no Si left in a 2mm ring at the edge while the initial edge trim width was 0.5mm only.

Process improvement

The FST profile and edge shape of the top wafer are characterized by using previously described metrology techniques. To enable a stable and robust via-last process and to realize multi-wafer stacking, the FST variation needs to decrease below 1μm and the lateral shrinkage needs to be minimized. The optimization of the wafer thinning process sequence is ongoing work by applying different hardware configurations, tuning the processes and validating whether requirements are met by using the same metrology techniques as described in this paper.


We have shown the capability of two complementary metrology tools to characterize the extreme wafer thinning process. This tool set can also be implemented to control the performance in a production environment at high throughput. Excursions can be analyzed further using techniques like in-line AFM. When thinning Si to 5μm and below for 3D-SOC integration technology schemes, multiple challenges arise where different measurement techniques are needed to characterize the final Si thickness across the full wafer. A good control of the final Si thickness as well as the total thickness variation (TTV) will become important when further scaling down 3D interconnects and increasing their density.


Authors would like to thank Fumihiro Inoue, Nina Tutunjyan, Stefano Sardo and Edward Walsby for supplying wafers to inspect and measure, for the interpretation and discussion of the results afterwards, and the early involvement of metrology in the process developments. This paper was previously published in the Proceedings of the 28th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2017), Saratoga Springs, NY, 2017, pp. 331-336.


1. A. Jourdain, “Extreme Wafer Thinning Optimization for Via-Last Applications,” 3DIC, November 2016.
2. F. Inoue, “Characterization of Extreme Si Thinning Process for Wafer- to-Wafer Stacking,” ECTC, May 2016.
3. K. Freischlad, S. Tang, and J. Grenfel, “Interferometry for wafer dimensional metrology,” Proceedings of SPIE, 6672, 667202 (2007).
4. P. Vukkadala, K. T. Turner, and J. K. Sinha, “Impact of Wafer Geometry on CMP for Advanced Nodes,” Journal of the Electro- chemical Society, 158(10), p. H1002 (2011).
5. L. Teugels, “Within-die and within-wafer CMP process characterization and monitoring using PWG Fizeau interferometry system,” ICPT, October 2016.
6. C. Mehanian et al., “Systems and Method for Simultaneously Inspecting a Specimen with Two Distinct Channels,” US Patent 7,782,452, issued August 2010.


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