BY DR. PHIL GARROU, Contributing Editor

It has been nearly a decade since Toshiba announced the use of backside TSV’s to miniaturize CMOS image sensors. More recently, In Feb 2017 at the IEEE Inter- national Solid-State Circuits Conference (ISSCC), Sony announced the Industry’s first 3-Layer Stacked CMOS Image Sensor (90nm generation back-illuminated CIS top chip, 30 nm generation DRAM middle chip, and a 40nm generation image signal processor (ISP) bottom chip for Smartphones. Sony further revealed that that the CIS is made in a 90 nm, 1 Al, 5 Cu technology, the DRAM is a 1 Gb, 30 nm (3 Al, 1 W) part, and the ISP is a 40 nm, 1 Al, 6 Cu device.

This newly developed sensor with stacked DRAM delivers fast data readout speeds, making it possible to capture still images of fast-moving subjects with minimal focal plane distortion as well as super slow motion movies at up to 1,000 frames per second (approx- imately 8x faster than conventional products) in full HD (1920×1080 pixels).

At the recent Mobile World Congress, Sony announced adoption of this technology their Xperia XZ Premium and XZs phones, with the Motion Eye camera system capable of 960 fps.

Dick James, writing in EE Times, reports on cross-sections of the rear-facing camera chip which contains the 3 layered stack. The CMOS image sensor (CIS) is mounted face-to-back on the DRAM, which is face-to-face with the image signal processor (ISP). The cross section below is direct for Sony. Since the DRAM is sandwiched between the CIS and the ISP, the high-speed data has to go through the memory chip to the ISP, and then back-and-forth until it is output through the I/F (interface) block of the ISP, at a conventional speed suitable for the applications processor” reports James who then adds that since the DRAM die also has the CIS row drivers on it, it must be “designed as a custom part, and is not one of the TSV-enabled (TSV = through-silicon via) commodity DRAMs.”

James has also shown the TSV layer connections between the two chips (see below). The cross section below shows two layers of TSVs connecting a 6-metal stack in the CIS to the M1 of the DRAM die. They did not have a cross-section of extended TSVs joining the CIS directly to the ISP, though there are TSVs through the DRAM to the top metal of the ISP.

In an interesting article by Ray Fontaine of TechInsights he notes that “the development of low-temperature wafer bonding and various wafer-to-wafer interconnect techniques have been key enablers for stacked image sensors. Two-die stacks, comprising a back-illumi- nated CIS and mixed-signal image signal processor (ISP), have emerged as the dominant configuration for leading smartphone camera chips. The CIS portion can be considered a ‘dumb’ chip carrying only an active pixel array. Most of the signal chain and digital processing is parti- tioned onto the ISP and systems appli- cation processor.”

The table compares technologies that have been implemented since 2013.

With Sony’s inclusion of DRAM into the CIS stack, I can safely predict that Omnivision and Samsung will not be far behind.