Yearly Archives: 2017

IC Insights has raised its IC market growth rate forecast for 2017 to 22%, up six percentage points from the 16% increase shown in its Mid-Year Update.  The IC unit volume shipment growth rate forecast has also been increased from 11% depicted in the Mid-Year Update to 14% currently.  As shown below, a large portion of the market forecast revision is due to the surging DRAM and NAND flash markets.

In addition to increasing the IC market forecast for this year, IC Insights has also increased its forecast for the O-S-D (optoelectronics, sensor/actuator, and discretes) market.  In total, the semiconductor industry is now expected to register a 20% increase this year, up five percentage points from the 15% growth rate forecast in the Mid-Year Update.

For 2017, IC Insights expects a whopping 77% increase in the DRAM ASP, which is forecast to propel the DRAM market to 74% growth this year, the largest growth rate since the 78% DRAM market increase in 1994.  After including a 44% expected surge in the NAND flash market in 2017, including a 38% increase in NAND flash ASP this year, the total memory market is forecast to jump by 58% in 2017 with another 11% increase forecast for 2018.

At $72.0 billion, the DRAM market is forecast to be by far the largest single product category in the semiconductor industry in 2017, exceeding the expected NAND flash market ($49.8 billion) by $22.2 billion this year. As shown in Figure 1, the DRAM and NAND flash segments are forecast to have a strong positive impact of 13 percentage points on total IC market growth this year. Excluding these memory segments, the IC industry is forecast to grow by 9%, less than half of the current total IC market growth rate forecast of 22% when including these memory markets.

Figure 1

Figure 1

IC Insights is set to release its October Update to The McClean Report.  The 30-page Update includes a detailed analysis of IC Insights’ revised forecasts for the IC, O-S-D, and total semiconductor markets through 2021.

The annual revenue from the global IC testing and packaging industry for 2017 is estimated to grow by 2.2% to reach US$51.73 billion, according to the latest research from TrendForce. Furthermore, providers of outsourced semiconductor assembly and test (OSAT) are projected to represent a share of 52.5% in the year’s total revenue.

The IC testing and packaging industry is expected to register recovery and growth in 2017 in contrast to the 2016 revenue result that showed a slight annual decline. This year, the main revenue driver has been the increase in the amount of IC components demanded for mobile devices. The strong demand for IC components has also expanded the deployment of advanced packaging solutions that offer higher levels of integration and higher numbers of I/O connections. In sum, the rising quantity and quality of demand during this year has benefited the IC testing and packaging industry revenue-wise.

The projected revenue ranking of the top 10 OSAT providers for 2017 is overall similar to the 2016 ranking. This year’s top three in sequence are ASE, Amkor and JCET. Among the top 10, PTI has gained enormously from the memory boom caused by the combination of tight market supply, application growth for high-performance computing and strong demand for high-density storage products. PTI also has the advantage of having a strong relationship with the memory giant Micron. TrendForce estimates that PTI’s annual revenue growth for this year will reach an impressive 26.3%, putting the company in the fifth place of the ranking.

osats

China’s IC backend service providers are focusing on developing their technologies as their progress in overseas mergers and acquisitions slows

TrendForce’s survey of the testing and packaging industry in 2017 also finds that there are now much fewer M&A targets for Chinese companies because of the increasing level of competition and consolidation activities in the global semiconductor sector. Furthermore, the barriers against Chinese companies for making overseas acquisitions using domestic capital have also been raised. Thus, Chinese IC backend service providers are shifting their focus away from trying to get technologies and market shares via overseas M&As. Instead, they are investing their resources in developing technologies related to fan-out processing and system-in-package (SiP) integration. They eventually want to get their solutions verified by potential clients, proving that they have the in-house expertise to be competitive in the market.

Chinese testing and packaging companies continue to gain processing capacity for packaging technologies that are high-end (e.g. flip chip and bumping) and more advanced (e.g. fan-in, fan-out, 2.5D interposer and SiP). Because of the progress in both technology development and M&As, Chinese service providers such as JCET, TSHT and TFME are projected to rise above the industry’s average in their revenue performances this year with double-digit growth rates.

Additionally, China’s IC testing and packaging industry will be supported by the growing number of domestic fabs in the coming year. TrendForce forecasts that China’s monthly 12-inch wafer capacity will increase by about 162,000 pieces before the end of 2018. This 180% increase from the current capacity level will give a sizable injection of demand into the domestic testing and packaging market.

 

An oversupply of polysilicon will double in 2018 despite strong demand in solar and semiconductor markets, according to a report Opportunities in The Solar Cell Market For Thin Film Technology, recently published by The Information Network (www.theinformationnet.com), a New Tripoli, PA-based market research company.

Consumption of polysilicon is booming as the semiconductor industry, particularly DRAM and NAND, is reaching record revenue and shipment growth. Solar installations are also growing strongly, increasing 35.5% in 2016.

Nevertheless, increased capacity put in place by polysilicon incumbents and capacity growth of Chinese manufactures pegged to increase 35% in 2017 is giving rise to an oversupply that will grow from 7.1% in 2016 to 15.0% in 2018.

As shown in the Table below, the industry will see an oversupply of 76,000 metric tonnes in 2018.

  2016 2018 2020
       
New PV (MW) 78,260 86,909 101,361
Inventory Requirement (MW) 3,913 4,345 5,068
Inventory % of demand 5% 5% 5%
Total PV Module Shipments (MW) 82,173 91,254 106,429
Efficiency loss 3% 3% 3%
Total PV Cell Shipments (MW) 84,638 93,992 109,622
Thin Film Supply (MW) 4,696 4,606 4,460
Polysilicon Consumed (Tonne/MW) 5 5 5
Total Solar Poly Required (MT) 423,696 464,804 546,845
Poly demand from Semis (MT) 34,180 40,119 39,044
Total Poly Demand (MT) 457,876 504,923 585,889
Poly Supply (MT) 490,250 580,910 640,453
Over Supply (MT) 32,374 75,987 54,564
% Over Supply 7.1% 15.0% 9.3%
Source: The Information Network (www.theinformationnet.com)

“In addition to polysilicon capacity increases, the transition from slurry wire slicing to diamond wire is creating more silicon wafers by reducing kerf loss, adding to the oversupply noted Dr. Robert Castellano, President of The Information Network.

The Information Network is a consulting and market research company addressing the semiconductor, LCD, HDD, and solar industries.

Praxair, Inc. (NYSE:PX), a global industrial gas company, has signed a long-term agreement to supply gaseous nitrogen to GLOBALFOUNDRIES in Malta, New York.

Praxair will build, own and operate a plant to support GLOBALFOUNDRIES’ advanced manufacturing processes at its Malta fabrication facility. GLOBALFOUNDRIES is a semiconductor foundry that provides design, development and fabrication services to technology companies, manufacturing chips for many of the top semiconductor companies in the world.

“With our rich history of supporting leading electronics customers worldwide, we are proud to grow Praxair’s existing relationship with GLOBALFOUNDRIES as they expand their chip manufacturing,” said Kevin Foti, president of Praxair’s U.S. industrial gases business. “As a result of this agreement, two companies with significant local New York operations are coming together and spurring growth in their businesses and the local economy as well. Our reliable supply of nitrogen and industry expertise will support GLOBALFOUNDRIES’ position as one of the leading semiconductor fabs in the world.”

“GLOBALFOUNDRIES continues to grow to meet the needs of our global customer base,” said Debra Leach, GLOBALFOUNDRIES senior director of Procurement. “A reliable supply of high-quality gaseous nitrogen is an important component of our manufacturing operation at Fab 8 in New York, especially as we expand capacity to meet demand for our leading-edge semiconductor technologies.”

Samsung Electronics Co., Ltd. announced today that 8-nanometer (nm) FinFET process technology, 8LPP (Low Power Plus), has been qualified and is ready for production.

The newest process node, 8LPP provides up to 10-percent lower power consumption with up to 10-percent area reduction from 10LPP through narrower metal pitch. 8LPP will provide differentiated benefits for applications including mobile, cryptocurrency and network/server, and is expected to be the most attractive process node for many other high performance applications.

As the most advanced and competitive process node before EUV is employed at 7nm, 8LPP is expected to rapidly ramp-up to the level of stable yield by adopting the already proven 10nm process technology.

“With the qualification completed three months ahead of schedule, we have commenced 8LPP production,” said Ryan Lee, Vice President of Foundry Marketing at Samsung Electronics. “Samsung Foundry continues to expand its process portfolio in order to provide distinct competitive advantages and excellent manufacturability based on what our customers and the market require.”

“8LPP will have a fast ramp since it uses proven 10nm process technology while providing better performance and scalability than current 10nm-based products,” said RK Chunduru, Senior Vice President of Qualcomm.

Details of the recent update to Samsung’s foundry roadmap, including 8LPP availability and 7nm EUV development, will be presented at the Samsung Foundry Forum Europe on October 18, 2017, in Munich, Germany. The Samsung Foundry Forum was held in the United States, South Korea and Japan earlier this year, sharing Samsung’s cutting-edge process technologies with global customers and partners.

 

To make continuous, strong and conductive carbon nanotube fibers, it’s best to start with long nanotubes, according to scientists at Rice University.

The Rice lab of chemist and chemical engineer Matteo Pasquali, which demonstrated its pioneering method to spin carbon nanotube into fibers in 2013, has advanced the art of making nanotube-based materials with two new papers in the American Chemical Society’s ACS Applied Materials and Interfaces.

The first paper characterized 19 batches of nanotubes produced by as many manufacturers to determine which nanotube characteristics yield the most conductive and strongest fibers for use in large-scale aerospace, consumer electronics and textile applications.

The researchers determined the nanotubes’ aspect ratio — length versus width — is a critical factor, as is the overall purity of the batch. They found the tubes’ diameters, number of walls and crystalline quality are not as important to the product properties.

Pasquali said that while the aspect ratio of nanotubes was known to have an influence on fiber properties, this is the first systematic work to establish the relationship across a broad range of nanotube samples. Researchers found that longer nanotubes could be processed as well as shorter ones, and that mechanical strength and electrical conductivity increased in lockstep.

The best fibers had an average tensile strength of 2.4 gigapascals (GPa) and electrical conductivity of 8.5 megasiemens per meter, about 15 percent of the conductivity of copper. Increasing nanotube length during synthesis will provide a path toward further property improvements, Pasquali said.

The second paper focused on purifying fibers produced by the floating catalyst method for use in films and aerogels. This process is fast, efficient and cost-effective on a medium scale and can yield the direct spinning of high-quality nanotube fibers; however, it leaves behind impurities, including metallic catalyst particles and bits of leftover carbon, allows less control of fiber structure and limits opportunities to scale up, Pasquali said.

“That’s where these two papers converge,” he said. “There are basically two ways to make nanotube fibers. In one, you make the nanotubes and then you spin them into fibers, which is what we’ve developed at Rice. In the other, developed at the University of Cambridge, you make nanotubes in a reactor and tune the reactor such that, at the end, you can pull the nanotubes out directly as fibers.

“It’s clear those direct-spun fibers include longer nanotubes, so there’s an interest in getting the tubes included in those fibers as a source of material for our spinning method,” Pasquali said. “This work is a first step toward that goal.”

The reactor process developed a decade ago by materials scientist Alan Windle at the University of Cambridge produces the requisite long nanotubes and fibers in one step, but the fibers must be purified, Pasquali said. Researchers at Rice and the National University of Singapore (NUS) have developed a simple oxidative method to clean the fibers and make them usable for a broader range of applications.

The labs purified fiber samples in an oven, first burning out carbon impurities in air at 500 degrees Celsius (932 degrees Fahrenheit) and then immersing them in hydrochloric acid to dissolve iron catalyst impurities.

Impurities in the resulting fibers were reduced to 5 percent of the material, which made them soluble in acids. The researchers then used the nanotube solution to make conductive, transparent thin films.

“There is great potential for these disparate techniques to be combined to produce superior fibers and the technology scaled up for industrial use,” said co-author Hai Minh Duong, an NUS assistant professor of mechanical engineering. “The floating catalyst method can produce various types of nanotubes with good morphology control fairly quickly. The nanotube filaments can be collected directly from their aerogel formed in the reactor. These nanotube filaments can then be purified and twisted into fibers using the wetting technique developed by the Pasquali group.”

Pasquali noted the collaboration between Rice and Singapore represents convergence of another kind. “This may well be the first time someone from the Cambridge fiber spinning line (Duong was a postdoctoral researcher in Windle’s lab) and the Rice fiber spinning line have converged,” he said. “We’re working together to try out materials made in the Cambridge process and adapting them to the Rice process.”

The 63rd annual IEEE International Electron Devices Meeting (IEDM), to be held December 2-6, 2017 at the Hilton San Francisco Union Square hotel, may go down as one of the most memorable editions for the sheer variety and depth of its talks, sessions, courses and events.

Among the most-anticipated talks are presentations by Intel and Globalfoundries, which will each detail their forthcoming competing FinFET transistor technology platforms in a session on Wednesday morning. FinFET transistors are a major driver of the continuing progress of the electronics industry, and these platforms are as important for their commercial potential as they are for their technical innovations.*

Each year at the IEDM, the world’s best technologists in micro/nano/bioelectronics converge to participate in a technical program consisting of more than 220 presentations, along with other events.

“Those who attend IEDM 2017 will find much that is familiar, beginning with a technical program describing breakthroughs in areas ranging from mainstream CMOS technology to innovative nanoelectronics to medical devices. The Sunday Short Courses are also a perennial favorite because they are not only comprehensive but are also taught by accomplished world experts,” said Dr. Barbara De Salvo, Scientific Director at Leti. “But we have added some new features this year. One is a fourth Plenary session, on Wednesday morning, featuring Nobel winner Hiroshi Amano. Another is a revamped Tuesday evening panel. Not only will it focus on a topic of great interest to many people, it is designed to be more open and less formal.”

Other features of the IEDM 2017 include:

  • Focus Sessions on the following topics: 3D Integration and Packaging; Modeling Challenges for Neuromorphic Computing; Nanosensors for Disease Diagnostics; and Silicon Photonics: Current Status and Perspectives.
  • A vendor exhibition will be held, based on the success of last year’s event at the IEDM.
  • The IEEE Magnetics Society will again host a joint poster session on MRAM (magnetic RAM) in the exhibit area. New for this year, though, is that the Society will also hold its annual MRAM Global Innovation Forum on Thursday, Dec. 7 at the same hotel, enabling IEDM attendees to participate. (Refer to the IEEE Magnetics Society website.) The forum consists of invited talks by leading experts and a panel discussion.

Here are details of some of the events that will take place at this year’s IEDM:

90-Minute Tutorials – Saturday, Dec. 2
These tutorials on emerging technologies will be presented by leading technical experts in each area, with the goal of bridging the gap between textbook-level knowledge and cutting-edge current research.

  • The Evolution of Logic Transistors Toward Low Power and High Performance IoT Applications, Dr. Dae Won Ha, Samsung Electronics
  • Negative Capacitance Transistors, Prof. Sayeef Salahuddin, UC Berkeley
  • Fundamental, Thermal, and Energy Limits of PCM and ReRAM, Prof. Eric Pop, Stanford University
  • Hardware Opportunities in Cognitive Computing: Near- and Far-Term, Dr. Geoffrey Burr, Principal Research Staff Member, IBM Research-Almaden
  • 2.5D Interposers and High-Density Fanout Packaging as Enablers for Future Systems Integration, Dr. Venkatesh Sundaram, Associate Director, Georgia Tech 3D Systems Packaging Research Center
  • Silicon Photonics for Next-Generation Optical Interconnects, Dr. Joris Van Campenhout, Program Director Optical I/O, Imec

Short Courses – Sunday, Dec. 3
The day-long Short Courses provide the opportunity to learn about important developments in key areas, and they enable attendees to network with the industry’s leading technologists.

Boosting Performance, Ensuring Reliability, Managing Variability in Sub-5nm CMOS, organized by Sandy Liao of Intel, will feature the following sections:

  • Transistor Performance Elements for 5nm Node and Beyond, Gen Tsutsui, IBM
  • Multi-Vt Engineering and Gate Performance Control for Advanced FinFET Architecture, Steve CH Hung, Applied Materials
  • Sub-5nm Interconnect Trends and Opportunities, Zsolt Tokei, Imec
  • Transistor Reliability: Physics, Current Status, and Future Considerations, Stephen M. Ramey, Intel
  • Back End Reliability Scaling Challenges, Variation Management, and Performance Boosters for sub-5nm CMOS,Cathyrn Christiansen, Globalfoundries
  • Design-Technology Co-Optimization for Beyond 5nm Node, Andy Wei, TechInsights

Merged Memory-Logic Technologies and Their Applications, organized by Kevin Zhang of TSMC, will feature the following sections:

  • Embedded Non Volatile Memory for Automotive Applications, Alfonso Maurelli, STMicroelectronics
  • 3D ReRAM: Crosspoint Memory Technologies, Nirmal Ramaswamy, Micron
  • Ferroelectric Memory in CMOS Processes, Thomas Mikolajick, Namlab
  • Embedded Memories Technology Scaling & STT-MRAM for IoT & Automotive, Danny P. Shum, Globalfoundries
  • Embedded Memories for Energy-Efficient Computing, Jonathan Chang, TSMC
  • Abundant-Data Computing: The N3XT 1,000X, Subhasish Mitra, Stanford University

Plenary Presentations – Monday, Dec. 4

  • Driving the Future of High-Performance Computing, Lisa Su, President & CEO, AMD
  • Energy-Efficient Computing and Sensing: From Silicon to the Cloud, Adrian Ionescu, Professor, EPFL
  • System Scaling Innovation for Intelligent Ubiquitous Computing, Jack Sun, VP of R&D, TSMC

Plenary Presentation – Wednesday, Dec. 6

  • Development of a Sustainable Smart Society by Transformative Electronics, Hiroshi Amano, Professor, Nagoya University. Dr. Amano received the 2014 Nobel Prize in Physics along with Isamu Akasaki and Shuji Nakamura for the invention of efficient blue LEDs, which sparked a revolution in innovative, energy-saving lighting. His talk will be preceded by the Focus Session on silicon photonics.

Evening Panel Session – Tuesday evening, Dec. 5

  • Where will the Next Intel be Headquartered?  Moderator: Prof. Philip Wong, Stanford

Entrepreneurs Lunch
Jointly sponsored by IEDM and IEEE EDS Women in Engineering, this year’s Entrepreneurs Lunch will feature Courtney Gras, Executive Director for Launch League, a local nonprofit focused on developing a strong startup ecosystem in Ohio. The moderator will be Prof. Leda Lunardi from North Carolina State University. Gras is an engineer by training and an entrepreneur by nature. After leaving her job as a NASA power systems engineer to work for on own startup company, she discovered a passion for building startup communities and helping technology-focused companies meet their goals. Named to the Forbes ’30 Under 30′ list in 2016, among many other recognitions and awards, Gras enjoys sharing her stories of founding a cleantech company with young entrepreneurs. She speaks on entrepreneurship, women in technology and clean energy at venues such as TEDx Budapest, the Pioneers Festival, and the IEEE WIE International Women’s Leadership Conference.

 

SEMI recently completed its annual silicon shipment forecast for the semiconductor industry. This SEMI forecast provides an outlook for the demand in silicon units for the period 2017–2019. The SEMI forecast shows polished and epitaxial silicon shipments totaling 11,448 million square inches in 2017; 11,814 million square inches in 2018; and 12,235 million square inches in 2019 (refer to table below). Total wafer shipments this year are expected to exceed the market high set in 2016 and are forecast to continue shipping at record levels in 2018 and 2019.

“Silicon shipment volumes are expected to ship at historic highs for this year and into 2019,” said Dan Tracy, senior director of Industry Research & Statistics at SEMI. “The expectation is for steady annual growth due to the proliferation of connected devices required for automotive, medical, wearables, and high-performance computing applications.”

2017 Silicon Shipment Forecast
(Millions of Square Inches, MSI)

Actual
Forecast
2015
2016
2017
2018
2019
MSI
10,269
10,577
11,448
11,814
12,235
Annual Growth
4.5%
3.0%
8.2%
3.2%
3.6%

Total Electronic Grade Silicon Slices* – Does not Include Non-Polished Wafers
Source: SEMI (www.semi.org), October 2017
*Shipments are for semiconductor applications only and do not include solar applications

Silicon wafers are the fundamental building material for semiconductors, which in turn, are vital components of virtually all electronics goods, including computers, telecommunications products, and consumer electronics. The highly engineered thin round disks are produced in various diameters (from one inch to 12 inches) and serve as the substrate material on which most semiconductor devices or “chips” are fabricated.

All data cited in this release is inclusive of polished silicon wafers, including virgin test wafers and epitaxial silicon wafers shipped by the wafer manufacturers to the end-users. Data do not include non-polished or reclaimed wafers.

On 14-17 November in Munich, SEMICON Europa will co-locate with productronica for the first time, for a focus on innovation and the future of the electronics manufacturing supply chain. Gathering key stakeholders from across the electronics manufacturing supply chain, the extensive range and depth, programs and networking events make the platform a necessity for players across the European electronics industry. SEMICON Europa will take place at Messe München Hall B1.

An Opening Ceremony will include a welcome speech by Ajit Manocha, president and CEO of SEMI, followed by Laith Altimime, president, SEMI Europe, plus four keynotes:

  • Bosch Sensortec: Stefan Finkbeiner, CEO, on how environmental sensing can contribute to a better quality of life in the context of the IoT
  • Rinspeed Inc.: Frank M. Rinderknecht, founder and CEO, on how to create innovative technologies, materials and mobility means of tomorrow
  • SOITEC: Carlos Mazure, CTO, executive VP, on contributions and benefits of engineered substrates solutions and thin-layer transfer technologies, focusing on applications in the smart space
  • TSMC Europe: Maria Marced, president, on opportunities for new business models to apply in the Smart City

“We are at the brink of a new wave of innovation ─ called the “Fourth Industrial Revolution” or “Smart Manufacturing.” It’s driven by connected devices and smart applications known as the IoT. This presents many opportunities for closer collaborations at global level, connecting key players, key ecosystems and building on the strengths of players in the value chain,” said Laith Altimime, president of SEMI Europe.

New programs on Flexible Electronics, Materials, and Automotive expand SEMICON Europa’s impact:

Returning programs include:

Register for programs before 12 November for a discount: http://www.semiconeuropa.org/register

SEMICON Europa offers free programs available on the exhibition show floor, including the TechARENA sessions ─ from MedTech to Lithography, Smart Manufacturing and Photonics, and many other topics.

For the fourth time at SEMICON Europa, INNOVATION VILLAGE will bring early-stage technology companies, the semiconductor industry’s top strategic investors, and leading technology partners together. This year sponsors include the City of Dresden and Volkswagen.

More than ever, there are unique opportunities to network with peers and connect with a large number of stakeholders at SEMICON Europa as attendees gather at the SEMICON CXO Luncheon, SEMI Member Breakfast, and SEMI Networking Night.

Connect! Register here and stay in touch via Twitter at http://www.twitter.com (use #SEMICONEuropa)

China IC industry outlook


October 17, 2017

SEMI, the global industry association and provider of independent electronics market research, today announced its new China IC Industry Outlook Report, a comprehensive report for the electronics manufacturing supply chain. With an increasing presence in the global semiconductor manufacturing supply chain, the market opportunities in China are expanding dramatically.

China is the largest consumer of semiconductors in the world, but it currently relies mainly on semiconductor imports to drive its growth. Policies and investment funds are now in place to further advance the progress of indigenous suppliers in China throughout the entire semiconductor supply chain. This shift in policy and related initiatives have created widespread interest in the challenges and opportunities in China.

With at least 15 new fab projects underway or announced in China since 2017, spending on semiconductor fab equipment is forecast to surge to more than $12 billion, annually, by 2018. As a result, China is projected to be the top spending region in fab equipment by 2019, and is likely to approach record all-time levels for annual spending for a single region.

Figure 1

Figure 1

This report covers the full spectrum of the China IC industry within the context of the global semiconductor industry. With more than 60 charts, data tables, and industry maps from SEMI sources, the report reveals the history and the latest industry developments in China across vast geographical areas ranging from coastline cities to the less developed though emerging mid-western regions.

The China IC industry ecosystem outlook covers central and local government policies, public and private funding, the industry value chain from design to manufacturing and equipment to materials suppliers. Key players in each industry sector are highlighted and discussed, along with insights into China domestic companies with respect to their international peers, and potential supply implications from local equipment and material suppliers. The report specifically details semiconductor fab investment in China, as well as the supply chain for domestic equipment and material suppliers.

Figure 2

Figure 2