Yearly Archives: 2017

Semiconductor Manufacturing International Corporation (“SMIC”; NYSE: SMI; SEHK: 0981.HK), the largest and most advanced foundry in mainland China, today announced the appointment of Dr. Haijun Zhao and Dr. Liang Mong Song as SMIC Co-CEO and Executive Director.

Dr. Zhao, age 54, was appointed as the Chief Executive Officer of the Company on May 10, 2017. Dr. Zhao joined the Company in October 2010 and was appointed as Chief Operating Officer and Executive Vice President in April 2013. In July 2013, Dr. Zhao was appointed as General Manager of Semiconductor Manufacturing North China (Beijing) Corporation, a joint venture company established in Beijing and a subsidiary of the Company. Dr. Zhao received his bachelor of science and doctor of philosophy degrees in electronic engineering from Tsinghua University (Beijing) and a master degree in business administration from the University of Chicago. He has 25 years of experience in semiconductor operations and technology development.

Dr. Liang Mong Song, age 65, graduated with a doctor of philosophy degree in electrical engineering from the Department of Electrical Engineering and Computer Sciences at the University of California, Berkeley. Dr. Liang has been engaged in the semiconductor industry for over 33 years, and was involved in memory and advanced logic process technology development. He owns over 450 patents and has published over 350 technical papers. He is a Fellow of Institute of Electrical and Electronic Engineers (IEEE).

Dr. Zixue Zhou, Chairman of SMIC, commented, “I am very pleased that Dr. Haijun Zhao and Dr. Liang Mong Song have joined the board of directors of SMIC as Executive Directors. I also warmly welcome Dr. Liang Mong Song to join SMIC together with Dr. Haijun Zhao to serve as Co-CEO. For decades Dr. Liang has focused on integrated circuit (“IC”) technology research and development and team management, with excellence and successful experience in advanced IC process development and management. His accession will further enhance SMIC’s ability to develop process technology and narrow the advanced technology gap between SMIC and its international peers; and at the same time, his efforts will further enhance SMIC’s ability to serve its customers and improve the metrics of SMIC’s existing technology. In addition, he brings corporate culture of top tier companies, which will enhance the company’s corporate culture to world class standards. It is believed with Dr. Haijun Zho and Dr. Liang Mong Song’s joint efforts SMIC will be led to a new height and make contributions to the development of IC industry.”

Dr. Haijun Zhao, Co-CEO of SMIC remarked, “I am pleased to join the board of directors of SMIC as Executive Director, and warmly welcome Dr. Liang Mong Song to join SMIC. Dr. Liang’s great achievements in the semiconductor industry are obvious to all. His accession will strengthen our management team, and as Co-CEO I am looking forward to working together with Dr. Liang. Together with our management and staff we will strive to make SMIC a global first-class IC enterprise.”

Dr. Liang Mong Song, Co-CEO of SMIC said, “I am greatly honored to take on the position of Co-CEO and Executive Director of SMIC, which to me, is not merely an opportunity, but also a challenge. SMIC’s rapid developments in recent years have been notable in the industry, and I am looking forward to working closely with the board of directors, Dr. Haijun Zhao and the management team to continuously improve the competitiveness of SMIC in the area of international IC manufacturing.”

sureCore Ltd. today announced it has joined the GLOBALFOUNDRIES (GF) FDXcelerator™ Partner Program and will make both their Low Power “PowerMiser” and Ultra Low Voltage “EverOn” SRAM offerings available on GF’s 22nm FD-SOI (22FDX®) process technology. PowerMiser delivers dynamic and static power savings exceeding 50 percent and 20 percent respectively. EverOn is the first commercially available SRAM to enable robust and reliable operation at near threshold voltages delivering hitherto unprecedented power savings. sureCore SRAMs are built from standard foundry bit cells and need no process modifications

“GF’s 22FDX is a logical next step for developers who are currently in 28nm bulk processes” said CEO Paul Wells. “We believe the 22FDX technology offers many technical and commercial benefits when compared to standard bulk CMOS technology. Combined with sureCore’s low power SRAM technology it will provide a best-in-class platform for the development of low power devices. In particular the EverOn SRAM will enable developers of IoT and Wearables the capability to deliver true near threshold operation by voltage scaling in tandem with the logic. Operation at as low as 550mV, the bit cell retention voltage, is a real game changer.”

“Our collaboration with sureCore enables customers to fully leverage the benefits of GF’s 22FDX platform and meet the ultra-low-power requirements of next generation connected devices,” said Alain Mutricy, senior vice president of product management at GF.

Key to the break-through is sureCore’s patented “smart-Assist” technology that allows robust operation down to the bit cell retention voltage. Other architectural improvements include enhanced sleep modes as well as array subdivision into four banks, each being independently controllable to be active, in retentive sleep or powered off thereby facilitating even greater power efficiency.

The challenges of near-threshold design drove sureCore to implement a world class verification and characterisation regime exploiting leading edge EDA tooling as well as extensive silicon validation using targeted process skews. Successful completion of industry standard High Temperature Operating Life (HTOL) tests has confirmed the inherent robustness and reliability of the EverOn SRAM.

“Low power design is placing new demands on SoC developers and, compared to the restrictions imposed by standard memory, our EverOn SRAM enables a new dimension in low power capability,” said Eric Gunn, sureCore’s COO.

The MIPI Alliance, an international organization that develops interface specifications for mobile and mobile-influenced industries, today announced the formation of an Automotive Birds of a Feather (BoF) Group to solicit industry input from original equipment manufacturers (OEMs) and their suppliers to enhance existing or develop new interface specifications for automotive applications. The group is open to both MIPI Alliance member and non-member companies to represent the broader automotive ecosystem.

Automobiles have become a new platform for innovation, and manufacturers are already using MIPI Alliance specifications as they develop and implement applications for passive and active safety, infotainment and advanced driver assistance systems (ADAS).MIPI interfaces such as Camera Serial Interface 2 (MIPI CSI-2SM), Display Serial Interface (MIPI DSISM) and Display Serial Interface 2 (MIPI DSI-2SM) are ideal for a variety of low- and high-bandwidth applications that integrate components such as cameras, displays, biometric readers, microphones and accelerometers. MIPI I3CSM helps automotive systems designers minimize the complexity, cost and development time for products that use multiple sensors in a space-constrained form factor. Highly sensitive, mission-critical automotive applications also benefit from MIPI interfaces’ low electromagnetic interference (EMI), a capability that’s been proven in billions of mobile phones and other handheld devices.

“Automakers already rely on MIPI Alliance’s industry-standard interfaces to enable a wide variety of applications, including collision mitigation and avoidance, infotainment and navigation,” said Matt Ronning, chair of the MIPI Alliance Automotive Subgroup and the Automotive BoF. “This call for participation helps ensure we cast a wide net to capture expertise to aid with extending existing and shape future MIPI specifications and collectively help realize the vision of how connected cars and automotive applications will evolve over the next decade. Just as mobile handset manufacturers benefited from the standardization that MIPI Alliance has provided, automotive OEMs would similarly benefit.”

“Active participation of automotive OEMs, tier-one and tier-two suppliers is greatly appreciated and necessary to, for example, work out the data link requirements between surround sensors, electronic control units, actors and displays for driver assistance and autonomous driving projects beyond 2020 and incorporate them into MIPI interface specifications,” said Uwe Beutnagel-Buchner, vice-chair of the MIPI Alliance Automotive Subgroup and the Automotive BoF.

For short-distance communications (< 0.3 meters), the MIPI CSI specification is the most widely adopted in automotive camera applications; MIPI DSI is rapidly gaining adoption also. The Automotive BoF Group’s initial focus will be to examine how MIPI specifications can potentially be extended to support communication link distances up to 15 meters, and at the same time support the high data rates associated with cameras and radar sensors for autonomous driving systems.

Join the MIPI Alliance Automotive BoF Group

The MIPI Automotive BoF is seeking additional qualified experts from OEMs, tier-one suppliers, component suppliers and related companies to provide key input into current and future MIPI interface specifications. The Automotive BoF is expected to convene via teleconference on a biweekly basis, with face-to-face meetings planned as necessary.

Companies already participating in MIPI Alliance’s Automotive BoF Group include: Analog Devices, Inc.; Analogix Semiconductor, Inc.; BitSim AB; BMW Group; Cadence Design Systems, Inc.; Continental Corporation; Etron Technology, Inc.; Ford Motor Company; Genesys Logic, Inc.; Hardent Inc.; Lontium Semiconductor Corporation; Microchip Technology Inc.; Mixel, Inc.; Mobileye, an Intel Company; NVIDIA; NXP Semiconductors; ON Semiconductor; Parade Technologies Ltd.; Qualcomm Incorporated; Robert Bosch GmbH; Sony Corporation; STMicroelectronics; Synopsys, Inc.; TE Connectivity Ltd.; Tektronix Inc.; Teledyne LeCroy; Texas Instruments Incorporated; Toshiba Corporation; Western Digital and others.

ArterisIP, the supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today announced it has joined the FDXcelerator Partner Program. This program enables SoC designers to integrate ArterisIP interconnect IP into their projects with the ability to accelerate the timing closure process for FDX-based designs. The partnership speeds the development of pioneering products in applications from automotive ADAS and machine learning to small IoT processors.

ArterisIP offerings participating in the FDXcelerator program include:

  • The Ncore Cache Coherent Interconnect IP with Ncore Resilience Package, which has been chosen by the industry’s leading automotive ADAS, autonomous driving, and machine learning SoC vendors for its power, performance, and area advantages and ISO 26262 functional safety features.
  • The FlexNoC Interconnect IP with FlexNoC Resilience Package, which is the backbone interconnect for most mobility and consumer electronics SoC designs where power consumption, performance, and cost are key design metrics.
  • The PIANO Timing Closure Package, which assists back-end timing closure with technology that works earlier in the SoC design flow, thereby reducing schedule risk.

“The addition of ArterisIP to the FDXcelerator Partnership Program has already realized benefits with the implementation of an FD-SOI automotive ADAS multi-processor SoC with fellow FDXcelerator partner Dream Chip Technologies,” said Alain Mutricy, senior vice president of product management at GF. “ArterisIP’s commitment to GF’s FDX technology enables a scalable on-chip interconnect IP technology that will help our customers meet stringent automotive safety requirements.”

“GF’s FDXcelerator program plays an important role for ArterisIP, enabling us to gain access to FD-SOI technology process and design information to enable improved automation of our interconnect timing closure assistance technology,” said K. Charles Janac, President and CEO of ArterisIP. “Interconnect timing closure assistance is becoming imperative as technologies like FD-SOI shrink feature sizes and allow ever-increasing transistor and wire densities.”

A new method that precisely measures the mysterious behavior and magnetic properties of electrons flowing across the surface of quantum materials could open a path to next-generation electronics.

Found at the heart of electronic devices, silicon-based semiconductors rely on the controlled electrical current responsible for powering electronics. These semiconductors can only access the electrons’ charge for energy, but electrons do more than carry a charge. They also have intrinsic angular momentum known as spin, which is a feature of quantum materials that, while elusive, can be manipulated to enhance electronic devices.

A team of scientists, led by An-Ping Li at the Department of Energy’s Oak Ridge National Laboratory, has developed an innovative microscopy technique to detect the spin of electrons in topological insulators, a new kind of quantum material that could be used in applications such as spintronics and quantum computing.

A new microscopy method developed by an ORNL-led team has four movable probing tips, is sensitive to the spin of moving electrons and produces high-resolution results. Using this approach, they observed the spin behavior of electrons on the surface of a quantum material. Credit: Saban Hus and An-Ping Li/Oak Ridge National Laboratory, U.S. Dept. of Energy

A new microscopy method developed by an ORNL-led team has four movable probing tips, is sensitive to the spin of moving electrons and produces high-resolution results. Using this approach, they observed the spin behavior of electrons on the surface of a quantum material. Credit: Saban Hus and An-Ping Li/Oak Ridge National Laboratory, U.S. Dept. of Energy

“The spin current, namely the total angular momentum of moving electrons, is a behavior in topological insulators that could not be accounted for until a spin-sensitive method was developed,” Li said.

Electronic devices continue to evolve rapidly and require more power packed into smaller components. This prompts the need for less costly, energy-efficient alternatives to charge-based electronics. A topological insulator carries electrical current along its surface, while deeper within the bulk material, it acts as an insulator. Electrons flowing across the material’s surface exhibit uniform spin directions, unlike in a semiconductor where electrons spin in varying directions.

“Charge-based devices are less energy efficient than spin-based ones,” said Li. “For spins to be useful, we need to control both their flow and orientation.”

To detect and better understand this quirky particle behavior, the team needed a method sensitive to the spin of moving electrons. Their new microscopy approach was tested on a single crystal of Bi2Te2Se, a material containing bismuth, tellurium and selenium. It measured how much voltage was produced along the material’s surface as the flow of electrons moved between specific points while sensing the voltage for each electron’s spin.

The new method builds on a four-probe scanning tunneling microscope–an instrument that can pinpoint a material’s atomic activity with four movable probing tips–by adding a component to observe the spin behavior of electrons on the material’s surface. This approach not only includes spin sensitivity measurements. It also confines the current to a small area on the surface, which helps to keep electrons from escaping beneath the surface, providing high-resolution results.

“We successfully detected a voltage generated by the electron’s spin current,” said Li, who coauthored a paper published by Physical Review Letters that explains the method. “This work provides clear evidence of the spin current in topological insulators and opens a new avenue to study other quantum materials that could ultimately be applied in next-generation electronic devices.”

Leti, a research institute of CEA Tech, will hold a workshop on Oct. 17 to present updates on their progress developing CoolCube high-density 3D sequential, monolithic-integration technology, and their supporting design-and-manufacturing ecosystems.

The workshop at the Hyatt Regency San Francisco Airport, Burlingame, Calif., is an official satellite event of the 2017 IEEE S3S conference. It will feature presentations from Leti and Qualcomm Technologies, Inc., a subsidiary of Qualcomm Incorporated, as well as partner firms, such as Applied Materials, SCREEN Semiconductor and HP Enterprise. Workshop attendees will include representatives of a growing ecosystem of design, manufacturing, and related companies.

As an extension of High Density 3D Cu-Cu/Hybrid Bonding Chip-to-Wafer/Wafer-to-Wafer Technologies, the CoolCube  concept enables stacking active layers of transistors in the third dimension, while coping with thermal budgets that do not degrade the performance of transistors or metal interconnects. Leti and Qualcomm have been collaborating for four years on various 3DVLSI advanced concepts, which have broad applications in low-power mobile devices and other IC platforms.

Workshop topics will include:

  • a review of 3DVLSI research at Qualcomm Technologies
  • an update on Leti’s technology and design
  • a complete Leti 3D-technologies landscape presentation, and
  • exploration of expectations and challenges around 3DVLSI technology.

The workshop is designed to encourage an active exchange of ideas among attendees on applications, markets, integration and other related areas.

Leti will highlight technological solutions available now for top-tier CMOS integration using CoolCube:

  • high-quality mono-crystalline channel
  • high-performance source/drain contacts
  • high-reliability gate stack and
  • low-parasitic stable intermediate back-end-of-line on 300mm wafers.

Leti this year taped out a test vehicle based on its internal technology and CoolCube circuit and will publish final results of the test in 2018. In this CMOS integration, the technology starts from 28nm foundry wafers and extends to current Leti top-tier processes. During the Oct. 17 workshop, Leti will present the next step: a newCoolCube tape-out, scheduled for mid-2018 and open to partners and collaborators. It is targeted to demonstrate by hardware promising applications enabled by CoolCube/3DVLSI.  Design contributions are already planned or expected in the following fields: neuromorphic, near-memory processing, high-performance FPGA and energy-efficient computing.

“As CoolCube has evolved, its development team has received a growing number of inquiries from companies and organizations all along the semiconductor value chain, including materials and equipment suppliers, electronic design automation (EDA) companies, fabless chipmakers and foundries, and assembly and test houses,” said Jean-Eric Michallet, Leti Head of Microelectronics Components Department. “Mutual cooperation will be an essential element of successful integration into high-volume production, and representatives of companies in these sectors are encouraged to attend the workshop.”

 

ClassOne Group, provider of semiconductor processing systems, today announced a special new financing program that seeks to give more attractive options to equipment purchasers.

ClassOne stated that the new financing program can eliminate the upfront cash outlay typically associated with equipment purchases, instead allowing more affordable and budgetable monthly payments. The new financing options will include capital leases, fair-market-value leases, term loans, payment deferrals and bridge-to-budget solutions. ClassOne has developed its new program in association with First American Vendor Finance, one of the nation’s largest and most highly respected equipment finance providers. The new financing program will be available both to current and future ClassOne customers.

“Our goal is to make it easier for users – especially budget-limited users – to acquire the tools and technology they need to achieve more profitable revenues,” said Byron Exarcos, CEO of ClassOne Group. “By integrating affordable new financing options directly into the equipment purchase process we can provide buyers with more attractive, more turnkey solutions – and put their new tools to work more quickly.”

The new financing program will be available both for ClassOne Technology and ClassOne Equipment purchases. ClassOne Technology provides new wet-chemical process tools specifically for ≤200mm wafer users, delivering advanced technology for the production of MEMs, power devices, RF, LEDs, photonics, sensors, microfluidics and other emerging technologies. ClassOne Equipment supplies the industry with certified high-quality refurbished systems, including major-name tools that cover a broad range of processing and metrology needs.

ClassOne Technology develops and produces innovative new wet-chemical equipment solutions that deliver advanced performance for the cost-conscious users of ≤200mm substrates.

With the prospects of large 450mm wafers going nowhere, IC manufacturers are increasing efforts to maximize fabrication plants using 300mm and 200mm diameter silicon substrates. The number of 300mm wafer production-class fabs in operation worldwide is expected to increase each year between now and 2021 to reach 123 compared to 98 in 2016, according to the forecast in IC Insights’ Global Wafer Capacity 2017-2021 report.

As shown in Figure 1, 300mm wafers represented 63.6% of worldwide IC fab capacity at the end of 2016 and are projected to reach 71.2% by the end of 2021, which translates into a compound annual growth rate (CAGR) of 8.1% in terms of silicon area for processing by plant equipment in the five-year period.

capacity install

Figure 1

The report’s count of 98 production-class 300mm fabs in use worldwide at the end of 2016 excludes numerous R&D front-end lines and a few high-volume 300mm plants that make non-IC semiconductors (such as power transistors).  Currently, there are eight 300mm wafer fabs that have opened or are scheduled to open in 2017, which is the highest number in one year since 2014 when seven were added, says the Global Wafer Capacity report.  Another nine are scheduled to open in 2018.   Virtually all these new fabs will be for DRAM, flash memory, or foundry capacity, according to the report.

Even though 300mm wafers are now the majority wafer size in use, both in terms of total surface area and in actual quantity of wafers, there is still much life remaining in 200mm fabs, the capacity report concludes.  IC production capacity on 200mm wafers is expected to increase every year through 2021, growing at a CAGR of 1.1% in terms of total available silicon area. However, the share of the IC industry’s monthly wafer capacity represented by 200mm wafers is forecast to drop from 28.4% in 2016 to 22.8% in 2021.

IC Insights believes there is still much life left in 200mm fabs because not all semiconductor devices are able to take advantage of the cost savings 300mm wafers can provide.  Fabs running 200mm wafers will continue to be profitable for many more years for the fabrication of numerous types of ICs, such as specialty memories, display drivers, microcontrollers, and RF and analog products.  In addition, 200mm fabs are also used for manufacturing MEMS-based “non-IC” products such as accelerometers, pressure sensors, and actuators, including acoustic-wave RF filtering devices and micro-mirror chips for digital projectors and displays, as well as power discrete semiconductors and some high-brightness LEDs.

Sun Chemical has entered into a license agreement to introduce a new family of molecular inks for the printed electronics market with Groupe Graham International (GGI), a world leader in user interface technologies in touch applications, and the National Research Council of Canada (NRC).

The new molecular ink technology developed by GGI and the NRC will be produced by Sun Chemical and promoted collaboratively by all three organizations. Based on ionic molecules processed through a reduction process, the new IPS family of products will offer a viable alternative to conventional polymer thick film conductive inks and serve as a low-cost alternative to nano materials.

The robust IPS family of products include silver and copper metallization options that can be applied by screen, inkjet or other high speed printing methods. The molecular inks feature sub-micron trace thickness that will enable the production of narrow traces in thin dielectric layers on a variety of applications, including: in-mold electronics (IME), printed antenna, displays, EMI/RFI and sensors.

“The IPS platform has been a multi-year development effort with the NRC and we are pleased to have its value validated by a global market leader,” said Eric Saint-Jacques, Chief Executive Officer at GGI. “We feel privileged to be working with Sun Chemical and look forward to supporting their global go-to-market initiatives with our solution design and manufacturing services.”

“We’re excited to help bring this innovative product line to the market,” said Roy Bjorlin, Global Commercial and Strategic Initiatives Director, Sun Chemical Advanced Materials. “Customers will be pleased to have an option in the marketplace that features fine lines for printed electronics. We look forward to collaborating with GGI and the NRC on this project.”

“We’re excited to enter the next phase of development,” said Thomas Ducellier, Executive Director, Printable Electronics Program, National Research Council of Canada.  “We look forward to seeing the unique attributes of the molecular ink platform address emerging market needs.”

GGI specializes in the design, engineering and manufacturing of customized electro-mechanical assemblies to deliver the optimal user interface for each specific context and environment.

By Zvi Or-Bach, President & CEO, MonolithIC 3D Inc.

Next week, as part of the IEEE S3S 2017 program, we will present a paper (18.3) titled “A 1,000x Improvement in Computer Systems by Bridging the Processor Memory Gap”. The paper details a monolithic 3D technology that is low-cost and ready to be rapidly deployed using the current transistor processes. In that talk, we will also describe how such an integration technology could be used to improve performance and reduce power and cost of most computer systems, suggestive of a 1,000x total system benefit. This game changing technology would be presented also in the CoolCube open workshop, a free satellite event of the conference 3DI program.

In an interesting coincidence DARPA just came out with a calls for >50x improvement in SoC

The 3DSoC DARPA solicitation reads: “As noted above, the 3DSoC technology demonstrated at the end of the program (3.5 Years) should also have the following characteristics:

–Capability of > 50X the performance at power when compared with 7nm 2D CMOS technology.

The 3DSoC program goal of 50x is to allow proposals suggesting US-built device at 90nm node vs. 7nm of computer chip using conventional 2D technologies. Looking at the table below we can see that if 7nm technology is used the benefit would be over 300x

darpa

This represents a paradigm shift for the computer industry and high-tech world, as normal scaling would provide 3x improvement at best. The emergence of AI and deep learning system makes memory access a key challenge for future systems, and indicate the far larger benefits offered by monolithic 3D integration.

The following charts were presented by the 3DSoC program manager Linton Salmon at the 3DSoC proposers day. The program calls for the use of monolithic 3D to overcome the current weakest link in computers – the memory wall.

darpa 2

Leading to the 3DSoC solicitation was work done by Stanford, MIT, Berkeley and Carnegie Mellon.

darpa 3

Proposals are due by Nov 6.

There is a unique opportunity to hear the 3DSoC DARPA Program Manager, Dr. Linton Salmon, articulate the program and what DARPA is looking for during his invited talk at the S3S 2017 conference next week.