Yearly Archives: 2017

Scientists have long searched for the next generation of materials that can catalyze a revolution in renewable energy harvesting and storage.

One candidate appears to be metal-organic frameworks. Scientists have used these very small, flexible, ultra-thin, super-porous crystalline structures to do everything from capturing and converting carbon into fuels to storing hydrogen and other gases. Their biggest drawback has been their lack of conductivity.

Now, according to USC scientists, it turns out that metal-organic frameworks can conduct electricity in the same way metals do.

This opens the door for metal organic-frameworks to one day efficiently store renewable energy at a very large, almost unthinkable scale.

The cobalt-based metal-organic framework used by the USC scientists, with purple representing cobalt, yellow representing sulfur and gray representing carbon. Credit: Smaranda Marinescu

The cobalt-based metal-organic framework used by the USC scientists, with purple representing cobalt, yellow representing sulfur and gray representing carbon. Credit: Smaranda Marinescu

“For the first time ever, we have demonstrated a metal-organic framework that exhibits conductivity like that of a metal. The natural porosity of the metal-organic framework makes it ideal for reducing the mass of material, allowing for lighter, more compact devices” said Brent Melot, assistant professor of chemistry at the USC Dornsife College of Letters, Arts & Sciences.

“Metallic conductivity in tandem with other catalytic properties would add to its potential for renewable energy production and storage” said Smaranda Marinescu, assistant professor of chemistry at the USC Dornsife College.

Their findings were published July 13 in the Journal of the American Chemical Society.

An emerging catalyst for long-term renewable energy storage

Metal-organic frameworks are so porous that they are well-suited for absorbing and storing gases like hydrogen and carbon dioxide. Their storage is highly concentrated: 1 gram of surface area provides the equivalent of thousands of square feet in storage.

Solar has not yet been maximized as an energy source. The earth receives more energy from one hour of sunlight than is consumed in one year by the entire planet, but there is currently no way to use this energy because there is no way to conserve all of it. This intermittency is intrinsic to nearly all renewable power sources, making it impossible to harvest and store energy unless, say, the sun is shining or the wind is blowing.

If scientists and industries could one day regularly reproduce the capability demonstrated by Marinescu, it would go a long way to reducing intermittency, allowing us to finally make solar energy an enduring and more permanent resource.

Metal or semiconductor: why not both?

Metal-organic frameworks are two-dimensional structures that contain cobalt, sulfur, and carbon atoms. In many ways, they very broadly resemble something like graphene, which is also a very thin layer of two-dimensional, transparent material.

As temperature goes down, metals become more conductive. Conversely, as the temperature goes up, it is semiconductors that become more conductive.

In the experiments run by Marinescu’s group, they used a cobalt-based metal-organic framework that mimicked the conductivity of both a metal and semiconductor at different temperatures. The metal-organic framework designed by the scientists demonstrated its greatest conductivity at both very low and very high temperatures.

GLOBALFOUNDRIES today unveiled AutoPro, a new platform designed to provide automotive customers a broad set of technology solutions and manufacturing services that minimize certification efforts and speed time-to-market. The company offers the industry’s broadest set of solutions for a full range of driving system applications, from informational Advanced Driver Assistance Systems (ADAS) to high-performance real-time processors for autonomous cars.

Today, the automobile semiconductor market is approximately $35 billion, and is expected to grow to an estimated $54 billion by 2023. This is driven by a need for new technologies that promise to enhance the driving experience such as navigation, remote roadside assistance and advanced systems that combine data from multiple sensors with high-performance processors that make control decisions.

“As vehicles move rapidly toward greater autonomy, auto manufacturers and parts suppliers are designing new ICs,” said Gregg Bartlett, senior vice president of the CMOS Business Unit at GF. “GF’s diverse automotive platform combines a range of technologies and services that meet the complexity and requirements for applications that enable connected intelligence for the automotive industry.”

Building on 10 years of automotive experience, the company’s AutoPro technology platform includes offerings in silicon germanium (SiGe), FD-SOI (FDX), CMOS and advanced FinFET nodes, combined with a broad range of ASIC design services, packaging and IP.

GF’s CMOS and RF solutions deliver an optimal combination of performance, integration and power efficiency for advanced sensors (radar, lidar, cameras), ADAS and autonomous processing (sensor fusion and AI compute) and body and powertrain control, with embedded eNVM technology for in-vehicle MCUs, as well as connectivity and infotainment systems. The company’s BCD and BCDLite® technologies provide high-voltage capabilities, with a path to supporting 48 volts that enable automotive power solutions for electric powertrain, Hybrid-electric (HEVs) and Internal Combustion Engine (ICE) vehicles.

These automotive solutions are available now, with additional access to quality and service across GF’s manufacturing fabs in the U.S., Europe, and Asia. GF AutoPro solutions support the full range of AEC-Q100 quality grades from Grade 2 to Grade 0.

AutoPro Service Package

In addition to GF’s technology platform, the company has initiated its AutoPro Service Package designed to ensure technology readiness, operational excellence and a robust automotive-ready quality system to continually improve quality and reliability throughout the product life-cycle.

GF’s Service Package builds on the company’s proven automotive quality and operational controls, providing customers access to the latest technologies which are designed to meet strict automotive quality requirements defined in the ISO, International Automotive Task Force (IATF), Automotive Electronics Council (AEC), and VDA (German) standards.

GF is currently working with major OEM customers and suppliers to develop and produce chips of the optimum quality and reliability as required by the various automotive applications.

Today, Intel announced the delivery of a 17-qubit superconducting test chip for quantum computing to QuTech, Intel’s quantum research partner in the Netherlands. The new chip was fabricated by Intel and features a unique design to achieve improved yield and performance.

The delivery of this chip demonstrates the fast progress Intel and QuTech are making in researching and developing a working quantum computing system. It also underscores the importance of material science and semiconductor manufacturing in realizing the promise of quantum computing.

Intel’s director of quantum hardware, Jim Clarke, holds the new 17-qubit superconducting test chip. (Credit: Intel Corporation)

Intel’s director of quantum hardware, Jim Clarke, holds the new 17-qubit superconducting test chip. (Credit: Intel Corporation)

Quantum computing, in essence, is the ultimate in parallel computing, with the potential to tackle problems conventional computers can’t handle. For example, quantum computers may simulate nature to advance research in chemistry, materials science and molecular modeling – like helping to create a new catalyst to sequester carbon dioxide, or create a room temperature superconductor or discover new drugs.

However, despite much experimental progress and speculation, there are inherent challenges to building viable, large-scale quantum systems that produce accurate outputs. Making qubits (the building blocks of quantum computing) uniform and stable is one such obstacle.

Qubits are tremendously fragile: Any noise or unintended observation of them can cause data loss. This fragility requires them to operate at about 20 millikelvin – 250 times colder than deep space. This extreme operating environment makes the packaging of qubits key to their performance and function. Intel’s Components Research Group (CR) in Oregon and Assembly Test and Technology Development (ATTD) teams in Arizona are pushing the limits of chip design and packaging technology to address quantum computing’s unique challenges.

About the size of a quarter (in a package about the size of a half-dollar coin), the new 17-qubit test chip’s improved design features include:

  • New architecture allowing improved reliability, thermal performance and reduced radio frequency (RF) interference between qubits.
  • A scalable interconnect scheme that allows for 10 to 100 times more signals into and out of the chip as compared to wirebonded chips.
  • Advanced processes, materials and designs that enable Intel’s packaging to scale for quantum integrated circuits, which are much larger than conventional silicon chips.

“Our quantum research has progressed to the point where our partner QuTech is simulating quantum algorithm workloads, and Intel is fabricating new qubit test chips on a regular basis in our leading-edge manufacturing facilities,” said Dr. Michael Mayberry, corporate vice president and managing director of Intel Labs. “Intel’s expertise in fabrication, control electronics and architecture sets us apart and will serve us well as we venture into new computing paradigms, from neuromorphic to quantum computing.”

Intel’s collaborative relationship with QuTech to accelerate advancements in quantum computing began in 2015. Since that time, the collaboration has achieved many milestones – from demonstrating key circuit blocks for an integrated cryogenic-CMOS control system to developing a spin qubit fabrication flow on Intel’s 300mm process technology and developing this unique packaging solution for superconducting qubits. Through this partnership, the time from design and fabrication to test has been greatly accelerated.

“With this test chip, we’ll focus on connecting, controlling and measuring multiple, entangled qubits towards an error correction scheme and a logical qubit,” said professor Leo DiCarlo of QuTech. “This work will allow us to uncover new insights in quantum computing that will shape the next stage of development.”

Advancing the quantum computing system

Intel and QuTech’s work in quantum computing goes beyond the development and testing of superconducting qubit devices. The collaboration spans the entire quantum system – or “stack” – from qubit devices to the hardware and software architecture required to control these devices as well as quantum applications. All of these elements are essential to advancing quantum computing from research to reality.

Also, unlike others, Intel is investigating multiple qubit types. These include the superconducting qubits incorporated into this newest test chip, and an alternative type called spin qubits in silicon. These spin qubits resemble a single electron transistor similar in many ways to conventional transistors and potentially able to be manufactured with comparable processes.

While quantum computers promise greater efficiency and performance to handle certain problems, they won’t replace the need for conventional computing or other emerging technologies like neuromorphic computing. We’ll need the technical advances that Moore’s law delivers in order to invent and scale these emerging technologies.

Intel is investing not only to invent new ways of computing, but also to advance the foundation of Moore’s Law, which makes this future possible.

The semiconductor IP market is expected to be valued at USD 6.22 billion by 2023, at a CAGR of 4.87% between 2017 and 2023, according to the new research report “Semiconductor IP Market by Design IP (processor IP, interface IP, memory IP), Source (royalty and licensing), vertical (consumer electronics, telecom, industrial, automotive, commercial), and Geography – Global Forecast to 2023,” published by MarketsandMarkets. The major factors driving this market include the advancement in multicore technology for consumer electronics sector, increasing demand for modern SoC designs leading to market growth, and growing demand for connected devices.

Consumer electronics to hold largest share of semiconductor IP market during forecast period

The increase in the use of consumer electronics in all the regions is boosting the growth of the semiconductor IP market for the consumer electronics vertical. Moreover, the markets for consumer electronic in APAC and RoW are expected to provide further growth opportunities for the market players as these regions are in a growing phase. In addition, APAC holds dominant share in the market for consumer electronics.

Processor IP to hold largest share of semiconductor IP market during forecast period

Owing to the increased demand for microprocessor, microcontroller, digital signal processor, and graphics processing unit across various verticals, the processor IP segment held the largest share of the semiconductor IP market in 2016, and it is expected to continue the same during the forecast period. The growth of the segment during the forecast period is attributed to the increasing application of processors in the telecom industry for 5G and in high-end cars. The market for processor IP for the automotive vertical is expected to grow at the highest CAGR between 2017 and 2023 due to increasing use of processors in advanced driver assistance systems (ADAS) and infotainment systems.

APAC to hold largest share of semiconductor IP market during forecast period

APAC held the largest share of the market in 2016 and is likely to dominate the semiconductor IP market with the largest market share during the forecast period as well. APAC is a major market for the consumer electronics, telecom, and automotive verticals. Also, this region has become a global focal point for large investments and business expansion opportunities. Moreover, the developments in electric vehicles are expected to provide an opportunity to the growth of the semiconductor IP market in China.

Toshiba Corporation (TOKYO:6502) today announced that its board of directors has approved a further investment by Toshiba Memory Corporation (TMC), a wholly-owned subsidiary that manufactures Flash memory, in manufacturing equipment for the Fab 6 clean room under construction at Yokkaichi Operations. TMC will invest approximately 110 billion yen as a second investment in Fab 6 for the installation of additional manufacturing equipment in the Phase-1 clean room.

Production at Fab 6 will be entirely devoted to BiCS FLASH, Toshiba’s innovative 3D Flash memory. As Toshiba announced in its August 3, 2017 release “Update on Toshiba Memory Corporation’s Investment in Production Equipment for Fab 6 at Yokkaichi Operations”, TMC has previously invested approximately 195 billion yen in Fab 6 as its first investment covering the installation of manufacturing equipment in the Phase-1 clean room and the construction of the Phase-2 clean room.

Demand for TMC’s next generation 3D Flash memory devices is expected to increase significantly due to growing demand for enterprise SSDs in datacenters, SSDs for PCs, and memory for smartphones; TMC expects this strong market growth to continue in 2018. TMC’s investment timing will position it to capture this growth and expand its business.

The investment in Fab 6 will enable TMC to install manufacturing equipment for 96-layer 3D Flash memories, including deposition and etching equipment.

There is no change in the FY2017 Financial Forecast announced on Aug 10, 2017, as the impact of the additional investment will be realized after FY2018. However, the FY2017 investment plan for Toshiba Corporation Storage & Devices Solutions Segment will be revised from 330 billion yen, as announced on August 10, to 400 billion yen by accelerating a part of the investment previously planned for FY2018. This will be used with the remaining 40 billion yen in the FY2017 investment plan, bringing this second investment to 110 billion yen. As announced on March 17, 2016 announcement “Notice of Construction of New Semiconductor Fabrication Facility,” Toshiba decided on a construction and equipment investment plan for the new fabrication facility, with an estimated cost of approximately 360 billion yen from FY2016 to FY2018. The company will update its investments plans to reflect any subsequent changes.

TMC has recently asked SanDisk, its collaborator in three joint ventures for investment in manufacturing equipment at TMC’s Yokkaichi Operations, whether it intends to jointly participate in this second investment for the Phase-1 clean room in the Fab 6 facility.

A research collaboration between Osaka University and the Nara Institute of Science and Technology for the first time used scanning tunneling microscopy (STM) to create images of atomically flat side-surfaces of 3D silicon crystals. This work helps semiconductor manufacturers continue to innovate while producing smaller, faster, and more energy-efficient computer chips for computers and smartphones.

Spatial-derivative STM images with 200x200 nm^2 at Vs = +1.5 V. Flat terraces become brighter and edges darker. The downstairs direction runs from left ((110) top-surface) to right ((-1-10) back-surface). Credit: Osaka University

Spatial-derivative STM images with 200×200 nm^2 at Vs = +1.5 V. Flat terraces become brighter and edges darker. The downstairs direction runs from left ((110) top-surface) to right ((-1-10) back-surface). Credit: Osaka University

Our computers and smartphones each are loaded with millions of tiny transistors. The processing speed of these devices has increased dramatically over time as the number of transistors that can fit on a single computer chip continues to increase. Based on Moore’s Law, the number of transistors per chip will double about every 2 years, and in this area it seems to be holding up. To keep up this pace of rapid innovation, computer manufacturers are continually on the lookout for new methods to make each transistor ever smaller.

Current microprocessors are made by adding patterns of circuits to flat silicon wafers. A novel way to cram more transistors in the same space is to fabricate 3D-structures. Fin-type field effect transistors (FETs) are named as such because they have fin-like silicon structures that extend into the air, off the surface of the chip. However, this new method requires a silicon crystal with a perfectly flat top and side-surfaces, instead of just the top surface, as with current devices. Designing the next generation of chips will require new knowledge of the atomic structures of the side-surfaces.

Now, researchers at Osaka University and the Nara Institute of Science and Technology report that they have used STM to image the side-surface of a silicon crystal for the first time. STM is a powerful technique that allows the locations of the individual silicon atoms to be seen. By passing a sharp tip very close to the sample, electrons can jump across the gap and create an electrical current. The microscope monitored this current, and determined the location of the atoms in the sample.

“Our study is a big first step toward the atomically resolved evaluation of transistors designed to have 3D-shapes,” study coauthor Azusa Hattori says.

To make the side-surfaces as smooth as possible, the researchers first treated the crystals with a process called reactive ion etching. Coauthor Hidekazu Tanaka says, “Our ability to directly look at the side-surfaces using STM proves that we can make artificial 3D structures with near-perfect atomic surface ordering.”

The same electrostatic charge that can make hair stand on end and attach balloons to clothing could be an efficient way to drive atomically thin electronic memory devices of the future, according to a new study led by researchers at the Department of Energy’s Lawrence Berkeley National Laboratory (Berkeley Lab).

In a study published today in the journal Nature, scientists have found a way to reversibly change the atomic structure of a 2-D material by injecting, or “doping,” it with electrons. The process uses far less energy than current methods for changing the configuration of a material’s structure.

Schematic shows the configuration for structural phase transition on a molybdenum ditelluride monolayer (MoTe2, shown as yellow and blue spheres), which is anchored by a metal electrodes (top gate and ground). The ionic liquid covering the monolayer and electrodes enables a high density of electrons to populate the monolayer, leading to changes in the structural lattice from a hexagonal (2H) to monoclinic (1T') pattern. Credit: Ying Wang/Berkeley Lab

Schematic shows the configuration for structural phase transition on a molybdenum ditelluride monolayer (MoTe2, shown as yellow and blue spheres), which is anchored by a metal electrodes (top gate and ground). The ionic liquid covering the monolayer and electrodes enables a high density of electrons to populate the monolayer, leading to changes in the structural lattice from a hexagonal (2H) to monoclinic (1T’) pattern. Credit: Ying Wang/Berkeley Lab

“We show, for the first time, that it is possible to inject electrons to drive structural phase changes in materials,” said study principal investigator Xiang Zhang, senior faculty scientist at Berkeley Lab’s Materials Sciences Division and a professor at UC Berkeley. “By adding electrons into a material, the overall energy goes up and will tip off the balance, resulting in the atomic structure re-arranging to a new pattern that is more stable. Such electron doping-driven structural phase transitions at the 2-D limit is not only important in fundamental physics; it also opens the door for new electronic memory and low-power switching in the next generation of ultra-thin devices.”

Switching a material’s structural configuration from one phase to another is the fundamental, binary characteristic that underlies today’s digital circuitry. Electronic components capable of this phase transition have shrunk down to paper-thin sizes, but they are still considered to be bulk, 3-D layers by scientists. By comparison, 2-D monolayer materials are composed of a single layer of atoms or molecules whose thickness is 100,000 times as small as a human hair.

“The idea of electron doping to alter a material’s atomic structure is unique to 2-D materials, which are much more electrically tunable compared with 3-D bulk materials,” said study co-lead author Jun Xiao, a graduate student in Zhang’s lab.

The classic approach to driving the structural transition of materials involves heating to above 500 degrees Celsius. Such methods are energy-intensive and not feasible for practical applications. In addition, the excess heat can significantly reduce the life span of components in integrated circuits.

A number of research groups have also investigated the use of chemicals to alter the configuration of atoms in semiconductor materials, but that process is still difficult to control and has not been widely adopted by industry.

“Here we use electrostatic doping to control the atomic configuration of a two-dimensional material,” said study co-lead author Ying Wang, another graduate student in Zhang’s lab. “Compared to the use of chemicals, our method is reversible and free of impurities. It has greater potential for integration into the manufacturing of cell phones, computers and other electronic devices.”

The researchers used molybdenum ditelluride (MoTe2), a typical 2-D semiconductor, and coated it with an ionic liquid (DEME-TFSI), which has an ultra-high capacitance, or ability to store electric charges. The layer of ionic liquid allowed the researchers to inject the semiconductor with electrons at a density of a hundred trillion to a quadrillion per square centimeter. It is an electron density that is one to two orders higher in magnitude than what could be achieved in 3-D bulk materials, the researchers said.

Through spectroscopic analysis, the researchers determined that the injection of electrons changed the atoms’ arrangement of the molybdenum ditelluride from a hexagonal shape to one that is monoclinic, which has more of a slanted cuboid shape. Once the electrons were retracted, the crystal structure returned to its original hexagonal pattern, showing that the phase transition is reversible. Moreover, these two types of atom arrangements have very different symmetries, providing a large contrast for applications in optical components.

“Such an atomically thin device could have dual functions, serving simultaneously as optical or electrical transistors, and hence broaden the functionalities of the electronics used in our daily lives,” said Wang.

A wide variety of laser technologies is today available to semiconductor manufacturers and enable the development of innovative semiconductor manufacturing processes. According to Yole Développement (Yole), the laser equipment market will grow at a 15% CAGR between 2016 and 2022 and should reach more than US$4 billion by 2022 (excluding marking). Those figures are showing the massive adoption of laser technologies for semiconductor manufacturing processes.
In its latest report titled Laser Technologies for Semiconductor Manufacturing, the market research and strategy consulting company details the status of this industry, mainly driven by dicing, via drilling and patterning in PCB flex and PCB HDI, IC substrates and semiconductor device processing.

The Laser Technologies for Semiconductor Manufacturing report from Yole provides a thorough analysis of the different existing laser equipment and laser source solutions developed for semiconductor process steps. It is a comprehensive analysis highlighting the maturity level of each laser type, based on a technical roadmap until 2022. With this new report, Yole’s analysts offer a clear understanding of the laser technologies’ benefits and added value for each manufacturing process.

illus_laser_technologies_manufacturing_markets_yole_oct2017

The Laser Technologies for Semiconductor Manufacturing report is the first of a wide collection of reports that will be released by Yole during the next months. Further its 1st Executive Forum on Laser Technologies taking place in Shenzhen, China, welcoming more than 100 attendees, the “More than Moore” market research and strategy consulting company Yole confirms the expansion of its activities towards the laser-based solutions. Technologies, roadmaps, market metrics, supply chain, competitive landscape, market shares and more. All these topics will be described and deeply analyzed in Yole’s laser technology & market reports.

Today, laser applications in the semiconductor industry are broad and diversified. Various laser technologies have started integrating into major semiconductor processes, including laser cutting, drilling, welding/bonding, debonding, marking, patterning, marking, measurement, deposition, driven by motherboards. They are used to process semiconductor devices, flexible and HDI PCBs , and in IC packaging applications.

Drivers of laser methods differ from one process step to another. However, there are similar and common drivers for applicability of lasers to semiconductor and PCB processing applications. The key trends driving laser applicability and contributing to its growth are:

   •  The desire for die size reduction and thus further miniaturization of devices driven by computers, hand-held electronic devices such as mobile phones, tablets and electronic book readers, wearable devices and consumer electronics.
•  Demand for increased yield and throughput.
•  Better die quality.
•  The need to inspect voids and particles through a transparent material such as glass, which requires the use of laser methods.
•  Laser annealing for very high flexibility.
However, the choice of the most suitable laser processing type depends strongly on the material to be processed, processing parameters, and the manufacturing process step.

Laser type is defined by parameters such as wavelength, emitting UV, green, or IR light, for example, as well as the duration of pulse, for example nanosecond, picosecond or femtosecond. Users must consider which pulse length and wavelength is right for their semiconductor process step and application.

Nanosecond lasers are the most commonly used type of laser applied in semiconductor manufacturing and PCB processing, with more than 60% market share. They are followed by picosecond, CO2 and femtosecond lasers. In the case of dicing step, the choice of laser type also depends on the material and substrate to be diced. For low dielectric constant (low-k) materials, nanosecond and picosecond UV lasers are used to optimize optical absorption. Picosecond and femtosecond IR lasers are typically used for cutting glass and sapphire substrates but not singulating SiC substrates.

In drilling, the type of laser employed depends on the substrate. Nanosecond UV lasers are usually employed in flexible PCBs, while CO2 lasers are largely applied for PCB HDI and IC substrates. However, for IC substrates, the choice between CO2 and nanosecond or picosecond UV lasers depends on via diameters. Below 20μm diameters, the industry tends to go to picosecond UV lasers which are much more expensive than nanosecond UV lasers but offer superior quality.

Generally speaking, CO2 is the cheapest and fastest laser solution and used in preference to nanosecond, picosecond or femtosecond solid state lasers for dicing, drilling, patterning, marking for applications that require high power and do not care about heat damage or dicing width. However, CO2 is limited when small features are needed. Nanosecond lasers are currently the dominant technology, but picosecond and femtosecond lasers could move ahead in the laser dicing equipment market. However, femtosecond laser implementation is more complex and expensive.

Yole’s laser report will provide a comprehensive overview of the laser equipment and laser sources used for each semiconductor process step application, along with a detailed analysis of laser technology trends and a market forecast. It will also offer a detailed analysis of the laser equipment market by volume and value, its growth for the 2016-2022 timeframe, and breakdown by laser type and process step application.

HEIDENHAIN CORPORATION announces the new appointment of David Fuson, Service Operations Manager for North America.

Fuson served for over 20 years in the U.S. Navy where he acquired a strong knowledge of rotating equipment and balancing of components, as well as expert level knowledge in operation, maintenance and repair of systems.  There, he managed repair and maintenance teams, and once Navy retired, continued to utilize his skills in the private sector at Flowserve Corporation where he served as Customer Service Manager instilling a shared, enthusiastic commitment to service.

Now at HEIDENHAIN, Fuson is responsible for overseeing daily service operations, including assisting supervisors, technicians and corporate group colleagues with customer escalations and expedited solutions as needed.  Putting the “Customer First”, Fuson has also recently implemented a HEIDENHAIN Hurricane Recovery Hotline to assist those customers in Texasand Florida who experienced equipment downtime due to those disasters.

“The HEIDENHAIN organization is a place where thoughts and ideas are encouraged, and where teamwork, collaboration and attention to detail are top priorities,” said Fuson.  “I am extremely fortunate to have been chosen for the role of Service Operations Manager here, and I commit to instilling and refreshing these values in the service department every day.”

HEIDENHAIN GmbH, headquartered in Traunreut, Germany, develops and supports motion control feedback solutions for the machine tool, semiconductor, electronics assembly and test, metrology, automation, medical, energy, biotechnology and other global markets.

Fujitsu Semiconductor Limited and ON Semiconductor (Nasdaq: ON) today announced an agreement that ON Semiconductor will purchase a 30 percent incremental share of Fujitsu’s 8-inch wafer fab in Aizu-Wakamatsu, resulting in 40 percent ownership when the purchase is completed. The purchase is scheduled to be completed on April 1, 2018, subject to certain regulatory approvals and other closing conditions.

The two companies entered into an agreement in 2014, under which ON Semiconductor obtained a 10 percent ownership interest in Fujitsu’s Aizu 8-inch fab. Initial transfers began in 2014, and successful production and ramp-up of wafers began in June 2015. ON Semiconductor continues to increase demand at the Aizu 8-inch fab, and both companies determined that further strategic partnership will maximize the value both companies provide.

ON Semiconductor plans to increase ownership to 60 percent by the second half of 2018 and to 100 percent in the first half of 2020, allowing ON Semiconductor to add capacity to their global footprint. This additional capacity will allow ON Semiconductor to continue scaling its business based on demand and enable increased supply chain flexibility.

“We believe that transforming into a globally competitive company is the key for the continuous growth of the Aizu 8-inch fab. Furthering our strategic partnership with ON Semiconductor, who provides a broad product portfolio, will enable the Aizu 8-inch fab to secure future growth,” said Kagemasa Magaribuchi, president of Fujitsu Semiconductor Limited. “We believe that the growth of the Aizu 8-inch fab will contribute to maintaining and expanding a strong workforce and assist with the development of the regions.”

“We have had a strong and successful partnership with Fujitsu since announcing our investment in 2014,” said Keith Jackson, president and CEO of ON Semiconductor. “We believe furthering our partnership with Fujitsu Semiconductor will enable us to maintain our industry-leading manufacturing cost structure and also help us optimize our capital spending in coming years. This is a strategic investment for ON Semiconductor to secure additional manufacturing capacity, in support of our accelerated production needs and for revenue growth in coming years.”

Manufacturing is a core competency for ON Semiconductor, and approximately 75 percent of manufacturing operations are done internally through the company’s industry leading cost structure.