Yearly Archives: 2017

Providing deep insights and perspectives on the challenges and opportunities in automotive electronics, the second edition of “FUTURECAR: New Era of Automotive Electronics Workshop” will be held November 8-10 at Georgia Tech in Atlanta, Georgia. SEMI (http://www.semi.org) and Georgia Tech, collaborators for the event, see unprecedented technical challenges and opportunities in electrical, mechanical and thermal designs, and new digital, RF, radar, LiDAR, camera, millimeter wave, high-power and high-temp technologies. The workshop will highlight rapid advancements in automotive electronics technologies and applications, and explore technical and business barriers and opportunities that are best addressed collectively across the supply chain.

The focus of the 2017 FUTURECAR workshop is on electronics in the car of the future. Autonomous driving, in-car smartphone-like infotainment, privacy and security, and all-electric cars will be among the topics presented, with particular emphasis on how these advancements impact devices and packaging with respect to materials, tools, processes, substrates, packages, components and integrated functions in R&D and in manufacturing. This event provides a unique opportunity for the semiconductor manufacturing and automotive supply chains to connect, collaborate and identify areas for new solutions.

The plenary session on November 8 will feature presentations from leading experts from Mercedes Benz, Porsche, Bosch, Qualcomm, SAE International and Yole Développement. The workshop sessions on November 9-10 include:

  • Power devices and packaging
  • High-temperature materials and reliability
  • Sensing electronics
  • Computing and communications
  • Student posters

FUTURECAR draws on the synergy between Georgia Tech in R&D and its industrial partners, as well as SEMI in global electronics manufacturing stewardship across the supply chain. Key to the depth of the workshop is support and expertise from the technical co-sponsors International Electronics Manufacturing Initiative (iNEMI), IEEE Electronics Packaging Society (IEEE EPS) and International Microelectronics Assembly and Packaging (IMAPS), as well as SAE International, the global association representing engineers and experts in the aerospace, automotive and commercial vehicle industries.

Workshop co-chairs are Prof. Rao Tummala, Georgia Tech; Bettina Weiss, SEMI; Grace O’Malley, iNEMI; Christian Hoffman (Qualcomm), IMAPS; and Patrick McCluskey, IEEE.

For more information on FUTURECAR 2017 and to register, please visit http://www.prc.gatech.edu/FUTURECAR

 

Applied Energy Systems (AES), provider of high and ultra high purity gas systems, services, and solutions – including design, manufacturing, testing, installation, and expert field service – is showcasing the capabilities of its SEMI-GAS® Xturion™ Blixer™ to support various processes that require forming gas mixtures. The Blixer™ provides a cost-effective alternative to purchasing expensive pre-mixed gas cylinders by enabling operators to blend their own mixtures on-site in their facility.

The ultra high purity gas mixing blender is used by customers across a diverse range of industries to uniformly mix H2 and N2 concentrations in customizable ratios that meet their distinct process requirements. Mixtures can be adjusted in real-time via the system’s GigaGuard™ PLC Controller, which features a 9” Siemens color touchscreen for intuitive operation, allowing the user to fine-tune formulations on demand. This makes the system particularly appealing for high volume applications, eliminating the need to stock a variety of pre-mixed forming gas concentrations, decreasing the frequency of cylinder change-outs, reducing tool downtime, increasing productivity, and ultimately providing the end user with a significant cost savings.

The Blixer™ system is designed to provide a continuous flow of precise gas blends and includes a static mixing tube and surge/mixing tank to address dynamic flow changes and effectively maintain mix tolerances. It is also equipped with a Thermal Conductivity Hydrogen Gas Analyzer, featuring auto-calibration capability and a low flow alarm, to ensure +/- 1% blending accuracy. Its PLC Controller includes Ethernet connectivity to allow for seamless integration with a facility’s Monitoring System, and the system’s hydrogen hazardous gas detector and automatic shutdown feature alert operators during undesirable system conditions.

“We have found the Blixer™ to be especially beneficial to customers using forming gas mixtures because it gives them flexibility to custom-blend H2/N2 concentrations in the exact ratios they desire—instead of investing in expensive pre-mixed cylinders that still may not be precisely mixed to their unique process requirements,” said Greg Havrilla, Technical Inside Sales Engineer for AES. “The system’s value spans industries. We’ve seen it support laser-based technology development, semiconductor fabrication, electrically-powered vehicle manufacturing, sustainable energy solutions, and a variety of industrial manufacturing applications. Its flexibility is reflected in its ability to satisfy a range of process-driven demands.”

AES-SEMI-GAS-Xturion-Blixer-System

By Dr. Jeongdong Choe, Senior Technical Fellow, TechInsights

There has been a great deal of speculation around the composition of Intel’s Optane™ XPoint memory technology: PCM or ReRAM, selector, layouts, patterning technology, technology node, multi-stacked cell structure, die floor plan, interconnection to each electrode (wordlines and bitlines), functional blocks, scalability and process integration.

TechInsights set about to find answers. We have analyzed Optane’s memory cell structure, materials, cell array and memory peripheral array design, layouts, process flow and circuitry. Our Advanced CMOS Essential (ACE) analyses on Intel’s XPoint memory presents our complete findings and market trend predictions. The following paragraphs present some of the highlights.

Intel XPoint memory is based on PCM and selector memory (storage) cell elements. GST-based PCM, Ge-Se-As-Si based Ovonic Threshold Switch (OTS) and two memory cell stacked array architecture are common across Intel’s and Micron’s XPoint technologies.

We examined effective memory cell area efficiency vs. memory array efficiency, and compared it to current DRAM and NAND products. In our previous analysis on XPoint memory die, we found that memory density per die is 0.62 Gb/mm2 and memory efficiency is over 91%. The memory array efficiency, however, may not represent the reality because the memory peripheral and CMOS circuitry cover most of the die area.

We can define the effective cell area efficiency as a ratio of the real area of the cell memory elements (storage) to the total die area. For example, the effective memory cell area efficiency on Toshiba 15 nm 2D planar NAND is 43.9% due to excluding BC, CSL, SSL, GSL dummy wordlines and peripheral area on a die, while memory array efficiency is 72%. Figure 1 shows comparison of the effective memory cell area efficiency for 2D/3D NAND products from Toshiba/SanDisk (Western Digital), Micron/Intel, SK Hynix and Samsung, and 3D XPoint (OptaneTM from Intel).

Figure 1. A comparison of effective memory cell area efficiency on 2D/3D NAND and XPoint memory

Figure 1. A comparison of effective memory cell area efficiency on 2D/3D NAND and XPoint memory

When it comes to the effective unit cell size per 1 bit, NAND flash devices have been scaled down from 2D NAND (320 nm2) to 48L 3D NAND (145.8 nm2) or even to 64L 3D NAND (88.5 nm2) for Toshiba NAND products, while Intel OptaneTM two cell stacked XPoint memory has 800 nm2 (effectively 2F2) (Figure 2).

Figure 2. A comparison of effective unit cell area per bit on 2D/3D NAND and XPoint memory

Figure 2. A comparison of effective unit cell area per bit on 2D/3D NAND and XPoint memory

A comparison of memory density with DRAM products shown in Figure 3 illustrates that XPoint has higher memory density (0.62 Gb/mm2) than Samsung 1x nm (0.19 Gb/mm2), SK Hynix 2y nm (0.15 Gb/mm2) and Micron 20 nm (0.094 Gb/mm2) DRAM dice. Micron announced that the memory density of XPoint would be ten times higher than commercial DRAM products. This is true if we compare it with 30 nm class DRAM products, because most of the 30 nm class DRAM products from major DRAM manufacturers have 0.06 Gb/mm2 memory density. The first commercial XPoint memory die has three times (vs. Samsung 1x DRAM) or six times (vs. Micron 20 nm DRAM) higher memory density than those of current DRAM products.

Figure 3. A comparison of die size and memory density on DRAM (25nm/20nm/18nm) and XPoint memory

Figure 3. A comparison of die size and memory density on DRAM (25nm/20nm/18nm) and XPoint memory

We found that Intel introduced some innovative and compelling technologies on their first XPoint products such as PCM/OTS stack used for memory elements, GST based PCM, Ge-Se-As-Si based OTS and carbon based conductor and 2-bit cell stacked memory array with three electrodes. Intel successfully used a 20nm SADP double patterning technology to build a very uniform GST-based PCM/OTS memory square/island. Complete details on the of TechInsights’ XPoint memory analysis can be found here.

Click here to hear more from Dr. Choe and his TechInsights colleagues on 3D NAND.

Today, SEMI announced the lineup of keynotes coming to SEMICON Japan’s “SuperTHEATER” ─ focusing on the future of the electronics manufacturing supply chain. SEMICON Japan 2017, the largest exhibition in Japan for electronics manufacturing, will take place at Tokyo Big Sight in Tokyo on December 13-15. Registration is now open for the exhibition and programs.

With the theme “Dreams Start Here,” SEMICON Japan 2017 will bring together the connections between people, technologies and businesses across the electronics manufacturing supply chain ─ extending to the internet of things (IoT) applications that inspire the dreams that shape the future.

Japan has the world’s third-largest 300mm wafer installed fab capacity and the world’s largest 200mm and smaller wafer fab capacity (including discrete devices production). Japan also supplies one third of the semiconductor equipment and more than half of the semiconductor materials that are purchased in the global market.

The SuperTHEATER offers nine keynote forums, all with simultaneous English-Japanese translation. On December 13, keynotes at SEMICON Japan’s SuperTHEATER include:

  • Opening Keynotes ─ Visions of the Game Changing Era
    • Soft Bank:  Ken Miyauchi, president and CEO, “The Information Revolution beyond the Singularity”
    • Qualcomm Technologies: Raj Talluri, senior VP of product management, “Qualcomm Viewpoint: Accelerating the Internet of Things”
       
  • Semiconductor Executive Forum ─ Growth Strategy in New Business Environment
    • TowerJazz Semiconductor: Russell Ellwanger, CEO, “Value Creation”
    • SMIC: Haijun Zhao, CEO, “Considerations in Developing Manufacturable IC Technologies”
    • Micron Technology: Wayne Allan, senior VP of global manufacturing, “Enabling Smart Manufacturing in Today’s Industry 4.0”

The SEMI Market Forum, also on December 13, will offer presentations from IHS Markit and SEMI, with the theme “In the Light and Shadow of Awaking China”

Additional SEMICON Japan 2017 highlights include:

  • IT/AI Forum on U.S. companies’ artificial intelligence strategies
  • IoT Global Trends Forum on semiconductors for IoT
  • IoT Key Technology Forum on Smart Transportation
  • Manufacturing Innovation Forum n “Manufacturing Technology for the Diversified Future”
  • Electronics Trends
  • Mirai (the Future) Vision

 

For more information and to register for SEMICON Japan, visit www.semiconjapan.org/en/

COMET Group, a global provider of high-quality systems, components and services such as x-ray, ebeam and radio frequency technologies, today announced the opening of Lab One, its customer-centric technology and application center in San Jose, CA.

Scheduled to open October 4th, Lab One will bring Comet Group’s three core technologies under one roof for the first time:

  • RF power – Comet Plasma Control Technologies (PCT) designs and manufactures the technology used to make semiconductors and is used by leading chip manufacturers that power the industry’s most popular mobile devices (e.g. Apple, Samsung) and electronics (e.g. flat panel displays)
  • X-ray – Yxlon’s industrial X-ray and computed tomography – systems and services enable customers to improve the quality of their products and processes by non-destructive testing, measuring and decision support in industries such as electronics, automotive, aerospace, medtech, science and new technologies. They are based on highly compact Comet x-ray components and sources
  • ebeam – ebeam technology inactivates harmful pathogens that can cause food borne illnesses and provides safe, environmentally friendly packaging materials that reduce waste and improve food security

The working Lab and testing environment will act as an extension to many leading Silicon Valley businesses – providing access to a variety of testing and inspection services, as well as opportunities to collaborate with Comet Group’s industry experts, who will be available for consultation, brainstorming and problem solving.

“Our new Lab One facility can save local businesses time by providing local inspection services, save them money by finding costly flaws, and solve their logistic inspection services headaches with quick answers to their non-destructive test needs,” said Paul Smith, Sr. Vice President at Comet Technologies USA. “It’s a place where ideas are jointly transformed into solutions and solutions into business success.” 

With pioneering solutions for a wide range of industries, Comet Group will support its clients by bringing greater safety and security, mobility, sustainability and efficiency to numerous areas of life.

By Yoichiro Ando, SEMI Japan

Shinzo Abe, the prime minister of Japan, plans to stage a Robot Olympics in 2020 alongside the summer Olympic Games to be hosted in Tokyo. Abe said he wants to showcase the latest global robotics technology, an industry in which Japan has long been a pioneer. Japan’s Robot Strategy developed by the Robot Revolution Initiative Council plans to increase Japanese industrial robot sales to 1.2 trillion JPY by 2020. This article discusses how the robotics industry is not just a key pillar of Japan’s growing strategy but also a key application segment that may lead Japan’s semiconductor industry growth.

Japan leads robotics industry

According to International Federation of Robotics (IFR), the 2015 industrial robot sales increased by 15 percent to 253,748 units compared to the 2014 sales. Among the 2015 record sales, Japanese companies shipped 138,274 units that represent 54 percent of the total sales according to Japan Robot Association (JARA). The robotics companies in Japan include Yaskawa Electric, Fanuc, Kawasaki Heavy Industries, Fujikoshi and Epson.

Source: International Federation of Robotics (global sales) and Japan Robot Association (Japan shipment)

Source: International Federation of Robotics (global sales) and Japan Robot Association (Japan shipment)

The automotive industry was the most important customer of industrial robots in 2015 that purchased 97,500 units or 38 percent of the total units sold worldwide. The second largest customer was the electrical/electronics industry (including computers and equipment, radio, TV and communication devices, medical equipment, precision and optical instruments) that showed significant growth of 41 percent to 64,600 units.

Semiconductors devices used in robotics industry

Robotics needs semiconductor devices to improve both performance and functionality. As the number of chips used in a robot increases and more advanced chips are required, the growing robotics market is expected to generate significant semiconductor chip demands.

FEA-RO-IA-R2000-SpotWeld-3

Semiconductor devices in robots are used for collecting information; information processing and controlling motors and actuators; and networking with other systems.

  • Sensing Devices: Sensors are used to collect information including external information such as image sensors, sound sensors, ultrasonic sensors, infrared ray sensors, temperature sensors, moisture sensors and pressure sensors; and movement and posture of the robot itself such as acceleration sensors and gyro sensors.

    Enhancing these sensors’ sensitivity would improve the robot performance. However, for robot applications, smaller form factors, lighter weight, lower power consumption, and real-time sensing are also important. Defining all those sensor requirements for a specific robot application is necessary to find an optimal and cost-effective sensor solution.

    In addition, noise immunity is getting more important in selecting sensors as robot applications expand in various environments that include noises. Another new trend is active sensing technology that enhances sensors’ performance by actively changing the position and posture of the sensors in various environments.

  • Data Processing and Motor Control Devices: The information collected by the sensors is then processed by microprocessors (MPUs) or digital signal processors (DSPs) to generate control signals to the motors and actuators in the robot. Those processors must be capable of operating real-time to quickly control the robot movement based on processed and analyzed information. To further improve robot performance, new processors that incorporate artificial intelligence (AI) and ability to interact with the big data cloud database are needed.
  • As robotics is adapted to various industry areas as well as other services and consumer areas, the robotics industry will need to respond to multiple demands. It is expected that more field programmable gate arrays (FPGAs) will be used in the industry to manufacture robots to those demands.

    In the control of motors and actuators, power devices play important roles. For precise and lower-power operation of the robot, high performance power devices using high band gap materials such as Silicon Carbide and Gallium Nitride will likely used in the industrial applications.

  • Networking Devices: Multiple industrial robots used in a production line are connected with a network. Each robot has its internal network to connect its components. Thus every robot is equipped with networking capability as a dedicated IC, FPGA or a function incorporated in microcontrollers.

Ando--industrial-automation

Smart Manufacturing or Industry 4.0 requires all equipment in a factory to be connected to a network that enables the machine-to-machine (M2M) communication as well as connection to the external information (such as ordering information and logistics) to maximize factory productivity. To be a part of such Smart Factories, industrial robots must be equipped with high-performance and high-reliability network capability.

Opportunities for semiconductor industry in Japan

Japanese semiconductor companies are well-positioned in the key semiconductor product segments for robotics such as sensors, microcontrollers and power devices. These products do not require the latest process technology to manufacture and can be fabricated on 200mm or smaller wafers at a reasonable cost. Japan is the region that holds the largest 200mm and smaller wafer fab capacity in the world and the lines are quite versatile in these product categories.

The robotics market will likely be a large-variety and small-volume market. Japanese semiconductor companies will have an advantage over companies in other regions because they can collaborate with leading robotics companies in Japan from early stages of development. Also, Japan may lead the robotics International Standards development which would be another advantage to Japanese semiconductor companies.

For more information about the robotics and semiconductor, attend SEMICON Japan on December 13 to 15 in Tokyo. Event and program information will be available at www.semiconjapan.org soon.

By James Amano, International Standards, SEMI

The SEMI International Standards Committee, at their SEMICON West 2017 meeting, approved the transformation of the existing 3D Stacked IC Committee and Assembly & Packaging Committee into a single, unified 3D Packaging and Integration Committee. Emerging technologies will be accommodated into the scope of the new committee, as North American TC Chapter Co-Chair Sesh Ramaswami (Applied Materials) explains: “Multi-die integration, horizontally and vertically, leveraging substrate, fan-out, interposer and TSV technology is our future. Hence, the new charter and scope will enable the committee to be of more value to the industry.”

Charter:

To explore, evaluate, discuss, and create consensus-based specifications, guidelines, test methods, and practices that, through voluntary compliance, will:

  • include the materials, piece parts, and interconnection schemes, and unique packaging assemblies that provide for the communication link between the semiconductor chip and the next level of integration, either single- or multi-chip configurations. It relates to the technologies for heterogeneous and other multi-chip packaging such as Fan-out/Fan-in Wafer Level Packaging, Panel Level Packaging, Three-Dimensional Stacking IC, device embedded packaging, flexible electronics technology
  • promote mutual understanding and improved communication between users and suppliers, equipment, automation systems, devices, and services
  • enhance the manufacturing efficiency, capability and shorten time-to-market and reduce manufacturing cost

Scope:

To develop standards for semiconductor devices, including processed wafers, chips, or multi-chip configurations to the next level of integration, either in single- or multi-chip configurations.

  • materials needed for 3D applications, including prime silicon and glass wafers, temporary and permanent bonding material, specifications needed for processed wafers and/or chips to enter an integration step, etc.
  • the materials related to the elements of, interconnection schemes, and unique packaging assemblies that provide for the communication link between device and packaging.
  • the technologies for heterogeneous and other multi-chip packaging such as Fan-out/Fan-in Wafer Level Packaging, Panel Level Packaging, Three-Dimensional Stacking IC, device embedded packaging, and flexible electronics technology
  • metrologies to support these 3D integration and packaging technologies

Masahiro Tsuriya (iNEMI), Japan Co-Chair, further emphasizes “The new 3D Packaging & Integration Committee will be able to contribute to the advance of new, innovative semiconductor packaging technologies.”

The global committee currently has chapters active in Japan, North America, and Taiwan, which all meet throughout the year. To get involved, please join the SEMI International Standards Program at: www.semi.org/standardsmembership.

Graphene is a sheet of carbon that is only one atom thick, and it has drawn worldwide attention as a new material. A research group from Kumamoto University, Japan has discovered that pressure can be generated by simply stacking graphene oxide nanosheets, a material that closely resembles graphene. They also found that the pressure can be increased by reducing the interlayer distance through heat treatment. It is an innovative approach for applying high pressure without using an enormous amount of energy.

The 2010 Nobel Prize in Physics was awarded to two scientists, Andre Geim and Konstantin Novoselov, for groundbreaking graphene experiments. The carbon material is very thin, strong, flexible, and has high electrical conductivity. Oxidized graphene nanosheets have many oxygen functional groups at the front and back of graphene, and previous research has shown that if several layers of oxidized graphene nanosheets are heat treated, the interlayer distance shrinks as oxygen functional groups are eliminated.

This led the researchers at Kumamoto University, Japan to consider that reducing the interlayer distance of graphene oxide nanosheets, could allow it to be used as a compressor that applies pressure to a substance sandwiched between the sheets. To measure pressure between nanosheets, they used molecular materials that change the electrical state of metal ions in response to pressure (spin crossover phenomenon). They observed an electrical state change of iron nanoparticles by sandwiching the material and measuring the spin crossover phenomenon between graphene oxide nanosheets.

As the interlayer distance becomes smaller, the pressure between layers rises. This means that the pressure value can be adjusted by the heat treatment temperature. The maximum pressure the researchers measured was 38 x 106 Pa (101,300 Pa at atmospheric pressure, or about 375 atm). Moreover, they found that pressure does not occur unless the nanosheets are properly stacked.

“There are several examples of special materials that cause compression by just sandwiching or wrapping, similar to our results here,” said Assistant Professor Ryo Ohtani of Kumamoto University, who led the study. “But, as far as we know, this graphene nanosheet is the first example in the world with the ability to adjust applied pressure by simply changing the heat treatment temperature. We expect that this “nano-compressor” will lead to new developments from fields such as material chemistry or physics. Particularly since this technique produces high pressures that normally cannot be obtained without adding a large amount of energy.”

Quantum dots are nanometre-sized semiconductor particles with potential applications in solar cells and electronics. Scientists from the University of Groningen and their colleagues from ETH Zürich have now discovered how to increase the efficiency of charge conductivity in lead-sulphur quantum dots. Their results will be published in the journal Science Advances on 29 September.

Quantum dots are clusters of some 1,000 atoms which act as one large ‘super-atom’. The dots, which are synthesized as colloids, i.e. suspended in a liquid like a sort of paint, can be organized into thin films with simple solution-based processing techniques. These thin films can turn light into electricity. However, scientists have discovered that the electronic properties are a bottleneck. ‘Especially the conduction of holes, the positive counterpart to negatively charged electrons’, explains Daniel Balazs, PhD student in the Photophysics and Optoelectronics group of Prof. Maria A. Loi at the University of Groningen Zernike Institute for Advanced Materials.

Stoichiometry

Loi’s group works with lead-sulphide quantum dots. When light produces an electron-hole pair in these dots, the electron and hole do not move with the same efficiency through the assembly of dots. When the transport of either is limited, the holes and electrons can easily recombine, which reduces the efficiency of light-to-energy conversion. Balazs therefore set out to improve the poor hole conductance in the quantum dots and to find a toolkit to make this class of materials tunable and multifunctional.

‘The root of the problem is the lead-sulphur stoichiometry’, he explains. In quantum dots, nearly half the atoms are on the surface of the super-atom. In the lead-sulphur system, lead atoms preferentially fill the outer part, which means a ratio of lead to sulphur of 1:3 rather than 1:1. This excess of lead makes this quantum dot a better conductor of electrons than holes.

Thin films

In bulk material, transport is generally improved by ‘doping‘ the material: adding small amounts of impurities. However, attempts to add sulphur to the quantum dots have failed so far. But now Balazs and Loi have found a way to do this and thus increase hole mobility without affecting electron mobility.

Many groups have tried to combine the addition of sulphur with other production steps. However, this caused many problems, such as disrupting the assembly of the dots in the thin film. Instead, Balazs first produced ordered thin films and then added activated sulphur. Sulphur atoms were thus successfully added to the surface of the quantum dots, without affecting the other properties of the film. ‘A careful analysis of the chemical and physical processes during the assembly of quantum dot thin films and the addition of extra sulphur were what was needed to get this result. That’s why our group, with the cooperation of our chemistry colleagues from Zürich, was successful in the end.’

Devices

Loi’s team is now able to add different amounts of sulphur, which enables them to tune the electric properties of the super-atom assemblies. ‘We now know that we can improve the efficiency of quantum dot solar cells above the current record of 11%. The next step is to show that this method can also make other types of functional devices such as thermoelectric devices.’ It underlines the unique properties of quantum dots: they act as one atom with specific electric properties. ‘And now we can assemble them and can engineer their electrical properties as we wish. That is something which is impossible with bulk materials and it opens new perspectives for electronic and optoelectronic devices.’

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Date: October 3, 2017 at 1 p.m. ET

Free to attend

Length: Approximately one hour

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Conventional planar flash memory technology is approaching critical scaling limitations that are driving the transition to 3D solutions. 3D NAND is expected to scale in height, from 16-bit-tall strings to string heights of more than 128 bits. Meanwhile NAND makers will find ways of placing these strings closer to each other through more aggressive lithography.

Join the analysts from TechInsights as they explore 3D NAND flash technology from a process, circuit and systems perspective.

Process

With the boom in 3D NAND technology over the last couple of years, all the major NAND manufacturers such as Samsung, Toshiba, Western Digital (SanDisk), Micron, Intel and SK Hynix have already released their cutting-edge 3D NAND commercial products with 64L. Compared to their previous 32L (or 36L) and 48L, memory density per unit cell array area reached up to 3.4 Gb/mm2 which is 2.7 times higher than 15 nm 2D NAND TLC. This year, the new QLC products were introduced, which further scaled development down to n+1 (96L) and n+2 (128L). Every NAND manufacturer keeps their own 3D NAND architecture, and we’ll explore them in more detail and discuss future 3D NAND technology trends and expectations.

Circuit

With the exception of the memory cell array layout, most 3D NAND flash manufacturers have similar on die peripheral circuit block arrangements, as seen in their previous planar NAND flash products, with the exception of Micron’s latest 32L flash product. In this portion of the presentation, we will look at 3D NAND die photographs and compare die cross sections to identify some of the major differences in circuit implementation and layout arrangements. Challenges in 3D NAND circuit extractions including metal line access for internal signal probing (waveform analysis), memory addressing and programming algorithms will also be discussed.

Systems

There are many similarities between implementations of SSDs, but it is their differences with the use of latest NAND flash devices (especially 3D NAND), that have become of great interest for systems analysis, and will be the topic for discussion in this segment. One of the latest systems analyzed by TechInsights showed many interesting new features and differences in operation, on even simple de-facto standard methods of operation, such as addressing a NAND flash device, as well as read-retry situations.

Speakers

Mohammad Ahmad, Architect

Mohammad Ahmad is an Engineering Solutions Architect in the IP Services group at TechInsights. He has extensive experience with the latest non-volatile semiconductor memory devices, and provides technical support and patent analysis to help global clients maximize the return on their intellectual property investments. Mohammad is responsible for leading, executing and managing large patent portfolio assessments to identify patents for assertion and divestiture and for determining and executing the required reverse engineering in support of the patent portfolios.

He specializes in reverse engineering including circuit extraction, functional testing and internal waveform probing of various semiconductor memories (NAND and NOR Flash, embedded and system memories, DRAM and SRAM). Patent claims analysis, evidence-of-use detection, claim chart documentation, prior art searches and patent/portfolio evaluation and mining.

Dr. Jeongdong Choe, Senior Technical Fellow

Jeongdong Choe is a Senior Technical Fellow for TechInsights. He has a Ph.D. in electronic engineering and over 26 years’ experience including 100+ filed/issued patents in semiconductor process integration for DRAM, (V) NAND, SRAM and logic devices. Prior to joining TechInsights in 2011, he worked as a Team Lead in R&D for SK-Hynix and Samsung where he optimized process and device architectures with state-of-the-art technologies for mass production.

Jeongdong has been a member of the ‘Future Technology Roadmap’ and ‘Patent Examination’ committees at Samsung, and has led a Process Consulting Group for advanced/emerging NVM devices such as STT-MRAM, ReRAM, and PCRAM and SOI/FinFET/HKMG device for 2x/1x nm future logic and memory devices. He has also written many articles including DRAM Makers Turn to New Process for Sub 2x/1x nm Cells, and Comparing Leading-Edge 2x/1x nm NAND Flash Memories. Jeongdong annually produces a widely distributed roadmaps for Memory Technology.

At Samsung, as Team Lead of NAND FLASH Process Architecture, he advanced next-generation devices, including 42 nm, 35 nm, 27 nm, 21 nm and 19 nm process nodes with optimized DPT (double patterning technology) for 3x and 2x devices and TPT (triple patterning technology) for 1x devices, as well as for sub-20 nm terabit generation for 3D-NAND, including TCAT and VG-NAND architecture.

Tarek Alhajj

Tarek Alhajj is an Engineering Solutions Architect in the Intellectual Property and Technical Services group at TechInsights where he creates solutions for complex technical and intellectual property problems, especially those involving memory systems.

In his previous role with the company, Tarek was an Engineering Analyst in the systems and software analysis group, where he performed in depth analysis of various circuits and systems, mostly within downstream products, through a combination of circuit extraction, electrical functional testing and literature research. He has analyzed and tested numerous commercial electronic devices for the purposes of intellectual property support, technical intelligence and research and development. His contributions to the development of reverse engineering and testing techniques, particularly for memories and memory systems such as NAND flash and SSDs, greatly enabled detailed analysis of complex systems. Tarek then moved on to Team Lead in the systems and software analysis group to lead and manage a team of engineers.

Prior to TechInsights, he worked for MOSAID Technologies as a Patent Licensing Engineer where he lead the portfolio management, including the due diligence, licensing and litigation of all flash memory and flash memory systems patent portfolios.

Tarek received a B.Eng. degree in Electrical Engineering from Carleton University, Ottawa, Canada, and an M.A.Sc. degree in Electrical Engineering from McGill University, Montreal, Canada. His studies and research focused mainly on characterization and system level behavioral modeling of complex mixed-signal circuits and systems.

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