Yearly Archives: 2017

A new system combines acoustic, optical and reflectometric techniques to enable measurement of metals, dielectrics, resists and critical dimensions on a single platform.

BY CHEOLKYU KIM, Director of Metrology Product Management, Rudolph Technologies, Inc.

Rapid growth in the mobile device market is generating demand for advanced packaging solutions with higher levels of system integration and increased I/Os and functionality. This demand is driving 2.5D/3D integration of IC devices, which in turn requires sophisticated packaging technologies. Among various approaches, fan-out is gaining traction as outsourced semiconductor assembly and test (OSAT) houses and wafer foundries roll out their own technologies. As illustrated in FIGURE 1, the adoption of fan-out technology accelerated significantly in 2016, and is projected to reach $2.5 billion by 2021, a more than 10X increase from 2015.

Screen Shot 2017-09-25 at 1.20.09 PM

First generation “core” fan-out was geared toward mobile applications and had RDL lines that were typically 10/10μm (line/space) and larger. Second generation HDFO processes, which were developed to integrate multiple chips in a single package, use more RDL lines at smaller width and tighter pitch, down to 2/2μm and smaller. Growth in HDFO accelerated with the entry of Apple and TSMC in 2016 and accounts for the bulk of the fan-out growth projected through 2021 [2-4].

As design rules for HDFO approach those of front-end processes, so too will requirements for process control and, in consequence, the need for more accurate and repeatable metrology. Until now, manufacturers have characterized metal films, such as RDL and under bump metallization (UBM), using semi-automated measurement tools, such as contact profilometers, which are easy to use and relatively inexpensive. However, these tools are not the best solution for measuring a variety of products with varying topographies in high volume production.

High Density Fan-Out process control

HDFO processes include one or more RDL, the number depending on the application. Like front-end processes, HDFO processes use additive and subtractive technol- ogies to create patterns of conductive metal lines isolated by dielectric materials. As RDL lines become smaller, controlling line resistance with appropriate dimensional control has become essential. For an RDL process, the most important parameters to monitor are dielectric thickness, Cu seed layer thickness, Cu thickness and line width (CD). In general, the process must operate inside a window that varies within 10% of the target value. This, in turn, requires measurement tools with a gauge capability (3σ repeatability + reproducibility) of 10% of the variability, or 1% of the target value. In addition to delivering accuracy and repeatability, the metrology system must be able to operate on product wafers and, therefore, 1) be able to measure test structures smaller than 50μm, 2) be non contact/non-destructive/ non-contaminating, 3) be fast enough to support high volume production and 4) be able to handle the significant surface topography and substrate/wafer warpage that are induced by the HDFO process.

As shown schematically in FIGURE 2, the metrology system described here (MetaPULSE® AP, Rudolph Technologies), combines picosecond ultrasonic laser sonar (PULSETM), automated optical microscopy and reflectometry to meet all the requirements for RDL process control in a single system. The acoustic technique, well proven and widely accepted for metal film metrology in front-end applications, is a first principle technology that provides accurate measurements of metal film thickness for UBM and RDL.

Screen Shot 2017-09-25 at 1.20.16 PM

Measurements of RDL thickness with this technique on dense line arrays, pads and bumps have shown excellent correlation to cross sectional scanning electron microscope (X-SEM) results. The precision and gage capability of the technology have been validated down to 2μm and meet OSAT and foundry RDL roadmap requirements.

The integration of a high-resolution reflectometer provides accurate measurements of dielectric and resist thickness, ranging from a few 1000Å to 60μm, on product wafers. The incorporation of an automated optical microscope/high-resolution camera provides gage-capable CD measurements. CD measurements can be made simultaneously with thickness measurements. The addition of optical CD measurements and reflectometer-based transparent film thickness measurements to the acoustic platform provides an efficient and comprehensive in-line RDL metrology solution that eliminates the need to route wafers to multiple measurement tools.

PULSE acoustic thickness measurements on opaque films

FIGURE 3 illustrates the principles of the PULSE acoustic measurement technology. An extremely short laser pulse is focused onto a small spot on the sample surface where the energy of the laser pulse is absorbed by the film surface. This causes a sudden increase of surface temperature, and rapid thermal expansion launches a sound wave on the surface that travels into the film. When the sound wave reaches an interface with an underlying film, it is partially reflected back to the surface as an echo. Upon arrival at the surface, the echo causes a change in optical reflectivity, which is detected to measure the round-trip travel time of the sound wave. Film thickness can be calculated from the travel time of the sound wave and the speed of sound in the material. Some of the energy from the original sound wave is transmitted through the interface. In a multi-layered stack, the progressing sound wave returns a distinct echo from each interface. An analysis of the round-trip travel time for each successive echo permits the calculation of the thickness of each layer. Typical data acquisition times vary from 1s to 4s per site. Repeatability is < 0.1% of target thickness, meeting the 10% GR&R requirement. FIGURE 4 shows the correlation between X-SEM and PULSE measurements for RDL in the 1.25μm-1.5μm thickness range. The excellent correlation clearly demonstrates the accuracy of PULSE thickness measurements.

Screen Shot 2017-09-25 at 1.20.23 PM Screen Shot 2017-09-25 at 1.20.30 PM Screen Shot 2017-09-25 at 1.20.36 PM

Reflectometer thickness measurements on transparent films

FIGURE 5 (left) demonstrates the strong correspondence between a measured reflectometer signal and a model fitted curve for 5μm polyimide on Si. The figure also shows the correlation between reflectometer measurements and a fab reference metrology tool. The excellent correlation with the reference tool confirms the accuracy of reflectometer measurements. Data collection time for reflectometer measurements is typically less than 1s. The reflectometer has excellent sensitivity with Å level resolution and gage-capable R&R.

Screen Shot 2017-09-25 at 1.20.44 PM Screen Shot 2017-09-25 at 1.20.49 PM

Automated optical CD measurements

Using the optical microscope/ high resolution camera system, users can define multiple regions of interest (ROI) for CD measurements, including single line and multi-line arrays. The built-in measurement algorithms can report individual or average values. Extension of the CD technique to also measure overlay has shown promising results and additional work is in progress to fully characterize the capability. FIGURE 6 shows images and signals from CD measurements on lines and arrays. The strong correlation between optical CD and X-SEM measurements (FIGURE 7) validates the accuracy of the technique. CD measurement with the optical microscope is limited by the micro- scope’s resolution, typically 1μm or larger. Since SEM resolution is typically on the scale of nanometers, the correlation requires proper calibration. The results shown in Fig. 7 are after calibration.

Screen Shot 2017-09-25 at 1.21.01 PM Screen Shot 2017-09-25 at 1.21.06 PM Screen Shot 2017-09-25 at 1.21.13 PM

Multi-layered stacks

Most of RDL plating requires prior deposition of a Cu seed layer, the thickness of which must also be tightly controlled. FIGURE 8 (left) shows examples of the acoustic signals acquired from three Cu/ Ti stacks of varying thickness. The first positive peak of each signal gives the round-trip travel time of the sound wave in the Cu film, while the spacing between first and second positive peaks gives the round-trip travel time through the Ti layer. The echo positions are used to calculate the thickness of Cu and Ti layers simultaneously. Figure 8 (right) shows the signal of an Au/Ni/Cu/Al stack measured on UBM. The echo from each layer is distinct. Knowing the arrival times of the echoes and the speed of sound in the materials, the system calculates the thickness of all four layers simultaneously, with 3σ repeatability less than 1% for each of the layers.

Screen Shot 2017-09-25 at 1.21.21 PM Screen Shot 2017-09-25 at 1.21.28 PM

Warped wafer handling

The thin wafers/substrates used in HDFO processes can be warped significantly at several different steps in the process, most significantly by the mismatch between thermal expansion coefficients of the molding compound and the die. Warpage of 2mm or more poses a major challenge to handling and measurement systems. A specially designed vacuum chuck has three concentric vacuum zones. Applying vacuum to the zones sequentially, starting with the innermost zone and working out, the chuck pulls and holds warped wafers flat against itself to allow accurate measurements.

Conclusions

High density fan-out packaging is essential for advancing growth in mobile and networking applica- tions. The integration of multi-chip modules in fan-out processes requires complex processing using tools and materials that are significantly more expensive than traditional packaging lines. We have described an automated metrology solution that combines acoustic measurements with high resolution reflectometry and optical microscopy to provide comprehensive, gage- capable measurements for characterizing critical process steps in high volume production applications. Simultaneous measurement of multiple parameters on a single platform eliminates the need to route product through several different tools, improving the speed and efficiency, and reducing the overall cost-of-ownership, of the metrology process.

References

1. “Fan-out technnologies and MarketTrends 2016 Report”,Yole Devel- oppement, July 2016
2. “What is driving advanced packaging platforms development?”, T. Buisson and S. Kumar, Chip Scale Review, pp. 32-36,May-June 2016 3. “Recent advances and trends in advanced packaging”, J. Lau, Chip
Scale Review, pp. 46-54, May-June 2017.
4. “Status of Advanced Packaging Report,” Yole Developpement, June 2017.

Synopsys, Inc. (NASDAQ: SNPS) today announced that the Synopsys Design Platform has been fully certified for use on Samsung Foundry’s 28FDS (FD-SOI) process technology. A Process Design Kit (PDK) and a comprehensive reference flow, compatible with Synopsys’ Lynx Design System, containing scripts, design methodologies and best practices is now available. For Samsung Foundry’s latest differentiated process offering, support for bias throughout the Design Platform flow has been thoroughly verified and certified to achieve optimal power and performance tradeoffs.

“FD-SOI technology offers one of the best power, performance, and cost tradeoffs,” said Jaehong Park, senior vice president of the Foundry Solutions Team at Samsung Electronics. “Samsung Foundry’s 28FD-SOI technology allows designs to operate both at high and low voltage making it ideal for IoT and mobile applications. Moreover, the FD-SOI technology exhibits the best soft error immunity, and, therefore, is well suited for applications that require high reliability such as automotive. Availability of certified Synopsys Design Platform, PDK and reference flow will allow our mutual customers to accelerate adoption of our 28FDS technology.”

“Our long standing, close collaboration with Samsung Foundry starts very early, allowing Synopsys to refine tools and flows enabling customers to achieve desired performance and power targets,” said Michael Jackson, corporate vice president of marketing and business development for the Design Group at Synopsys. “Certification of the Synopsys Design Platform, complete with PDK and reference flow helps our mutual customers to rapidly design with confidence for Samsung Foundry’s 28-nm FD-SOI process.”

Advancements in spintronics


September 25, 2017

Applications now include nanoscale Spintronics sensors that further enhance the areal density of hard disk drives, through MRAMs that are seriously being considered to replace embedded flash, static random access memories (SRAM) and at a later stage dynamic random access memories (DRAM).

BY HIDEO OHNO, MARK STILES, and BERNARD DIENY, IEEE

Spintronics is the concept of using the spin degree of freedom to control electrical current to expand the capabilities of electronic devices. Over the last 10 years’ considerable progress has been made. This progress has led to technologies ranging from some that are already commercially valuable, through promising ones currently in development, to very speculative possibilities.

Today, the most commercially important class of devices consists of magnetic sensors, which play a major role in a wide variety of applications, a particularly prominent example of which is magnetic recording. Nonvolatile memories called magnetic random access memories (MRAMs) based on magnetic tunnel junctions (MTJs), are commercial products and may develop into additional high impact applications either as standalone memories to replace other random access memories or embedded in complementary metal–oxide–semiconductor (CMOS) logic.

Some technologies have appealing capabilities that may improve sensors and magnetic memories or develop into other devices. These technologies include three- terminal devices based on different aspects of spin-transfer torques, spin-torque nano-oscillators, devices controlled by electric fields rather than currents, and devices based on magnetic skyrmions. Even further in the future are Spintronics-based applications in energy harvesting, bioinspired computing, and quantum technologies.

But before we get into detail about where Spintronics is today, we need to cover the history of Spintronics.

The history of spintronics

Spintronics dates to the 1960s and was discovered by a group at IBM headed by Leo Esaki, a Japanese physicist who would later go on to win a share of the Nobel Prize I 1973 for discovering the phenomenon of electronic tunneling. Esaki and his team conducted a study which showed an antiferromagnetic barrier of EuSe sandwiched between metal electrodes exhibits a large magnetoresistance.

Subsequent advances of semiconductor thin film deposition techniques such as molecular beam epitaxy led to the development of semiconductor quantum structures, which prompted studies of magnetic multilayers. Ensuing studies of magnetic multilayers resulted in the discovery of giant magne- toresistance (GMR) in 1988. This effect was used to make magnetic sensors, which boosted the areal density of information stored on hard disk drives and led to the 2007 Nobel Prize in Physics awarded to Albert Fert and Peter Grunberg.

Since then rapid progress has continued to enhance both the role and the potential of Spintronics. So, let’s take a look at where we are now.

Where we are now

Applications now include nanoscale Spintronics sensors that further enhance the areal density of hard disk drives, through MRAMs that are seriously being considered to replace embedded flash, static random access memories (SRAM) and at a later stage dynamic random access memories (DRAM). Applica- tions also include devices that utilize spin current and the resulting torque to make oscillators and to transmit information without current.

Now let’s look at those applications and more in-depth.

Modern Hard Disk Drives: Two breeds of Spintronics sensors have replaced traditional anisotropic magnetoresistance (AMR) sensors. Those sensors include giant magnetoresistance (GMR) sensors (used in hard disk drives between 1998 and 2004) and tunnel magnetoresistance (TMR) sensors (used since 2004).

Those sensors are part of the technology development that enabled the increase of storage density of hard disk drives by several orders of magnitude, laying the foundation of today’s information age in the form of data centers installed by the cloud computing industry.

Magnetoresistive Random Access Memory (MRAM): MRAM and particularly spin-transfer- torque MRAM (STT-MRAM) is a nonvolatile memory with very high endurance and scalability. The current STT-MRAM technology uses an array of MTJs with an easy axis of magnetization oriented out of the plane of the layers. These MTJs utilize interface perpendicular anisotropy at the CoFeB–MgO interface, along with the large TMR of the system, for reading the state of magnetization. The spin-transfer torque exerted by a spin polarized current is used to change the magneti- zation direction, offering an efficient way of rewriting the memory. FIGURE 1 show the main families of MRAM that have evolved since 1995.

Screen Shot 2017-09-25 at 12.26.37 PM

 

Screen Shot 2017-09-25 at 12.26.43 PM

Three Terminal Magnetic Memory Devices: Recent physics developments raise the prospect of three- terminal spintronic memory devices. These devices have an advantage over the standard two-terminal devices used in memory applications such as MRAM in that separating the read and write functions poten- tially overcomes several future roadblocks in the devel- opment of MRAM. There are two writing schemes: one is based on spin currents generated by an electrical current running through a heavy metal adjacent to the free layer of the MTJ. The current causes a spin current both in the bulk of the heavy metal and at the interface; this spin current then exerts a torque, called the spin-orbit torque, on the magnetization. In this scheme, the write current does not pass through the MTJ, separating the write and read functions. The other scheme uses current-induced domain wall motion to move a domain wall in the free layer of the MTJ from one side of the fixed layer to the other. In this scheme, the current passes through the free layer, but not the tunnel barrier, again separating the read and write functions.

Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing: Spintronic-based nonvolatile embedded working memory used in conjunction with CMOS-based logic applications is a crucial first step toward standby-power-free logic circuits that are much needed for Internet of Things (IoT) applications. MRAM based logic-in-memory reduces the overhead of having memory and logic apart and gives both minimized interconnection delay and nonvolatility.

Security: These devices have shown great promise for logic and memory applications due to their energy efficiency, very high write endurance, and nonvolatility. Besides, these systems gather
many entropy sources which can be advantageously used for hardware security. The spatial and temporal randomness in the magnetic system associated with complex micromagnetic configurations, the nonlinearity of magnetization dynamics, cell-to-cell process variations, or thermally induced fluctuations of magnetization can be employed to realize novel hardware security primitives such as physical unclonable functions, encryption engines, and true random number generators.

Spin-Torque and Spin-Hall Nano-Oscillators: Spin-torque nano-oscillators (STNO) and spin-Hall effect nano-oscillators (SHNO) are in a class of miniaturized and ultra-broadband microwave signal generators that are based on magnetic resonances in single or coupled magnetic thin films. These oscil- lators are based on magnetic resonances in single or combined magnetic thin films where magnetic torques are used to both excite the resonances and subsequently tune them. The torques can be either spin-transfer torques due to spin-polarized currents (STNOs) or spin Hall torques due to pure spin currents (SHNOs). These devices are auto-oscillators and so do not require any active feedback circuitry with a positive gain for their operation. The auto-oscillatory state is strongly nonlinear, causing phase– amplitude coupling, which governs a wide range of properties, including frequency tunability, modulation, injection locking, mutual synchronization, but also causes significant phase noise. STNOs and SHNOs can, in principle, operate at any frequency supported by a magnetic mode, resulting in a potential frequency range of over six orders of magnitude, from below 100 MHz for magnetic vortex gyration modes to beyond 1 THz for exchange dominated modes. Since STNOs and SHNOs can also act as tunable detectors over this frequency range, there is significant potential for novel devices and applications.

Beyond the applications listed, the spin degree of freedom is also being used to convert heat to energy through the spin Seebeck effect, to manipulate quantum states in solids for information processing and communication, and to realize biologically inspired computing. These may lead to new develop- ments in information storage, computing, communication, energy harvesting, and highly sensitive sensors. Let’s take a look at these new developments.

Thermoelectric Generation Based on Spin Seebeck Effects: The study of combined heat and spin flow, called spin caloritronics, may be used to develop more efficient thermoelectric conversion. Much of the focus of research in spin caloritronics has been the longitudinal spin Seebeck effect, which refers to spin-current generation by temperature gradients across junctions between metallic layers and magnetic layers. The generated spin current in the metallic layer gets converted into a charge current by the inverse spin Hall effect, making a two-step conversion process from a thermal gradient perpen- dicular to the interface into a charge current in the plane of the interface. This process can be used for thermoelectric conversion. Device structures using the spin Seebeck effect differ significantly from those using conventional Seebeck effects due to the orthog- onality of the thermal gradient and resulting charge current, giving different strategies for applications of the two effects.

Electric-Field Control of Spin-Orbit Interaction for Low-Power Spintronics: Control of magnetic properties through electric fields rather than currents raises the possibility of low energy magnetization reversal, which is needed for low-power electronics and Spintronics. One specific way to accomplish this low energy switching is through electric-field control of electronic states leading to modification of the magnetic anisotropy. By applying a voltage to a device, it is possible to change the anisotropy such that the magnetization rotates into a new direction. While such demonstrations of switching alone are not sufficient to make a viable device, voltage controlled reversal is a promising pathway toward low-energy nonvolatile memory devices.

Control of Spin Defects in Wide-Bandgap Semiconductors for Quantum Technologies: The spins in deep level defects found in diamond (nitrogen- vacancy center) and in silicon carbide (divacancy) have a quantum nature that manifests itself even at room temperature. These can be used as extremely sensitive nanoscale temperature, magnetic-field, and electric-field sensors. In the future, microwave, photonic, electrical, and mechanical control of these spins may lead to quantum networks and quantum transducers.

Spintronic Nanodevices for Bioinspired Computing: Bioinspired computing devices promises low-power, high-performance computing but will likely depend on devices beyond CMOS. Low-power, high performance bioinspired hardware relies on ultrahigh- density networks built out of complex processing units interlinked by tunable connections (synapses). There are several ways in which spin-torque-driven MTJs, with their multiple, tunable functionalities and CMOS compatibility, are very well adapted for this purpose. Some groups have recently proposed a variety of bioin- spired architectures that include one or several types of spin-torque nanodevices.

Skyrmion-Electronics: An Overview and Outlook: The concept of skyrmions derives from high energy physics. In magnetic systems, skyrmions are magnetic textures that can be viewed as topological objects. Theory suggests that they have properties that might make them useful objects in which to store and manip- ulate information. Many of the ideas are similar to ideas that were developed decades ago for bubble memory or, more recently, racetrack memory. There are several possible advantages for skyrmion devices as compared to other related devices. They are potentially higher density and lower energy, although the arguments for these remain to be experimentally verified.

So, what does the future of spintronics have in store?

The future

Spintronics will continue to have increasing impact, but the future is somewhat uncertain. The importance of magnetic sensors is likely to remain important while the importance of the magnetic sensors in hard disk drives appears to depend on the economics of mass storage in the cloud.

MRAM seems likely to play an increasing role both as standalone memory and embedded in CMOS. The degree of adoption still depends on a few technical and many economic considerations. The acceleration, over the past few months, of announcements and demonstrations related to STT-MRAM produced by major microelectronics companies, seems to indicate that large volume production of STT-MRAM is getting quite close. If the adoption of this technology by microelectronics industry becomes a reality, the whole field will be strongly boosted.

In the future, Spintronics can play a critical role in areas such as IoT, ultralow-power electronics, high-performance computing (HPC). Besides, in the next 10 to 15 years, we are likely to see a much greater role played by alternative forms of computing. The role that Spintronics plays in those technologies is likely to be strongly influenced by the success of MRAM. If MRAM is successful, we will have developed the ability to manufacture it making it easier to import into other technologies.

Some of the recent technical developments that have significant virtues for applications will likely play a role in technology 10 to 15 years from now but many will not. Research on many of these ideas will continue and will spawn related areas. Material research is key along this road.

Innovative materials allowing efficient charge to spin and spin to charge current conversion, or good control of magnetic properties by voltage, or efficient injection/manipulation/detection of spins in semicon- ductors can play major roles. Along with this idea, the use of oxide materials in spintronic devices can become quite important. Oxides share crystal- linity with semiconductors in distinction to metallic magnetic devices. Will the greater control that comes with crystallinity give advantages to oxides in future devices? These are some of the many topics that are likely to be addressed in the coming years.

DSA and EUV should be envisioned as complementary, not competing, techniques that will eventually become mainstream for fine-pitch lithography.

BY DOUGLAS J. GUERRERO, Ph.D., Brewer Science, Rolla, MO

Advances in lithography have always been critical in the drive toward each subsequent semiconductor node. Anticipating limitations in the scaling ability of immersion lithography, the industry has been pursuing next-generation lithography techniques. Several techniques have been proposed, including extreme ultraviolet (EUV) lithography, multibeam electron-beam lithography, nanoimprint lithography and directed self-assembly (DSA) of block copolymers.

DSA attracted a great deal of interest from major semiconductor manufacturers for several years, following its initial development in the early 2000s. However, it has since fallen out of favor to some extent, in part because of advances in EUV lithography as a result of focused investment in that technology. Recent developments in DSA materials and processing promise to overcome concerns that have delayed its implementation.

Choosing an appropriate lithography technique does not need to be an either-or proposition. The greatest opportunity may lie in leveraging both EUV lithography and DSA. Although these two technologies are sometimes seen as competing, it makes more sense to envision them as complementary. This article explains how lithography may benefit by taking advantage of both EUV and DSA, and why previously existing roadblocks may no longer pose obstacles.

The material defines the pattern

Unlike most lithography techniques, where the mask defines the pattern, in DSA the pattern exists in the material itself. The original block copolymers (BCPs) for DSA combine polystyrene (PS) and poly(methyl methacrylate) (PMMA), two polymers that naturally segregate themselves into separate phases. Adjusting the relative proportions of PS and PMMA in the PS-b-PMMA material changes the morphology from spherical to cylindrical to lamellar (FIGURE 1). The product of the Flory interaction parameter, χ, and the segment length determine the spacing of the ordered structure. The higher the value of χ, the finer the pitch of the resulting structure.

Screen Shot 2017-09-22 at 12.38.34 PM

Standard PS-b-PMMA materials have relatively low χ, which limits the pitch to 20nm or larger. Some materials manufacturers are considering chemistries other than PS-b-PMMA to produce high-χ BCPs, replacing the PMMA component with polydimethylsiloxane or polyhydroxystyrene. Modifying PS-b-PMMA is another approach to increase χ. In this manner, it is possible to tune χ, the molecular weight and the glass transition temperature to achieve lamellar spacing between 14nm and 40nm under various annealing conditions.

The process flow for BCP deposition is straightforward. A neutral layer spin-coated onto the substrate allows for the BCP to separate into its individual domains during the thermal annealing process. The neutral layer allows for domain separation because it does not have affinity for either of the polymer chains in the BCP. Polymer domain separation is responsible for pattern formation.

Processing considerations

The DSA deposition process uses one of two basic approaches (FIGURES 2 and 3). Graphoepitaxy leverages topography to align the BCPs, depositing them into relatively deep trenches. Guide patterns define the trenches, confining the BCPs into configurations in which they align in a preferred direction. Chemical epitaxy, or chemoepitaxy, is based on a chemical pattern on a flat substrate, on top of which the BCPs self-align.

Screen Shot 2017-09-22 at 12.38.43 PM

Click to enlarge.

The semiconductor industry is pursuing both graphoepitaxy and chemoepitaxy approaches, favoring the former for producing fine-pitch vias and the latter for creating arrays of parallel lines.

Annealing temperatures are in the range of 250°C to 275°C, making them compatible with standard semiconductor processing. The annealing step can be lengthy—up to two hours to create structures with sufficiently low defect rates—adding cost to the process.

PS-b-PMMA BCPs are being manufactured in high- volume quantities. Worldwide, 1.1 million tons of the material are currently in use for a variety of applica- tions. This quantity is greater than the needs of the entire semiconductor industry. Therefore, although no commercially produced DSA materials are currently targeted for semiconductor applications, the infra- structure is in place to scale up production of suitable materials when the industry is ready.

Why DSA is attractive now

DSA was added to the ITRS roadmap in 2007. Major semiconductor industry players originally believed DSA would enter commercial production anywhere between the 14nm and 7nm logic nodes, and even sooner for DRAM; but so far that has not come to pass. A survey at the 2016 DSA Symposium suggested that the technology is still not ready for the mainstream and won’t be for several years. But some IDMs would like to accelerate the process, and there are reasons to believe this is not only possible, but desirable.

Decreasing the wavelength to 193nm immersion lithography has enabled line width and spacing down to 80nm. Techniques such as self-aligned quadruple patterning (SAQP) can create even smaller features through multiple lithography/etch iterations, but at the expense of adding lithography steps, each requiring a custom mask.

Immersion lithography is reaching its limits, providing an opportunity for next-generation lithographic techniques. Designs with critical dimensions (CD) in the range of 10nm to 30nm create a sweet spot for these state-of-the-art techniques.

Advances in EUV lithography are one factor that has led the industry to favor it over DSA. Today’s EUV materials have greater sensitivity compared with older- generation products, therefore requiring lower UV doses; and line roughness has improved as well. EUV lithography can create vias with 30nm or 40nm spacing that are not feasible with immersion lithography.

DSA enables even finer resolution than the semicon- ductor industry currently demands. Feature sizes are just now approaching a level where DSA can be especially effective. If these trends continue, the technique is poised to be widely adopted before the end of this decade.

DSA and EUV: Better together?

The most effective solution may lie in leveraging EUV and DSA technologies to take advantage of the strengths of each. Both methods can achieve resolution levels that are compatible with the N7 and N5 logic nodes. EUV lithography is well-suited to patterning designs with multiple different pitches, down to line width and spacing around 30nm. For such fine pitches, however, the number of mask steps required may make the technique prohibitively expensive. Local CD uniformity (LCDU) can also be a concern, especially at high throughput rates.

The initial hard-mask lithography process is the same for both EUV and DSA, but they diverge during pattern processing. Once the BCPs are deposited, DSA can achieve 30nm feature size without requiring additional masks. Annealing naturally separates the two phases into the correct morphology. The DSA process, however, is best suited to designs with a single pitch.

EUV can be used to pattern lower-resolution features on a chip, plus create spacers for subsequent DSA deposition. This combination provides the greatest design flexibility while streamlining the fabrication process, eliminating processing steps and reducing mask costs. LCDU is also better than with EUV alone.

DSA is best suited for devices with multiple repeating, regular fine-pitch features. Therefore, it likely will first be implemented in DRAM storage, later migrating to use in via layers on logic devices. Graphoepitaxy, especially using EUV to deposit the spacers, can enable more complex designs using DSA, where different regions of the chip require different pitches. This will presumably be the approach of choice for logic chips.

Despite the promise that leveraging both DSA and EUV offers, the semiconductor industry will only migrate to this approach once suppliers can convince IDMs that the materials have overcome their technical limita- tions. DSA has suffered from several challenges that have delayed its adoption: Primary issues are defectivity, pattern placement accuracy, ease of integration into manufacturing flows, and cost. But there is reason to be optimistic, as advances in chemistry and processing methods are improving all these metrics.

Overcoming technical challenges

The 2016 DSA Symposium survey identified defec- tivity as the greatest technical challenge. Defectivity and cost are related, in that the lowest defect levels are seen with the longest annealing times. While annealing for as little as five minutes causes the two phases to separate, the resulting material contains far too many defects to be suitable for commercial use.

Wafers are typically annealed one at a time, which can make the cost of annealing prohibitive. However, recent research using batch annealing in a vertical furnace showed great promise for reducing cost. By annealing 150 wafers in parallel for 30 minutes, researchers were able to demonstrate sufficiently low defect levels at a cost lower than that of SAQP.

Using both DSA and EUV has the potential to alleviate the problem of pattern placement errors. For example, EUV lithography can create prepatterned holes for doublet vias. The two vias may merge during the EUV process but will then automatically separate during DSA. Without DSA, an additional lithography step may be required to avoid merged vias.

This approach of leveraging EUV and DSA for fine- pitch vias is most reliable when the via shape is optimized. Studies have shown that a peanut shape, rather than an elliptical one, is ideal for creating doublet vias with minimal risk for pattern placement errors, even at the challenging N5 node.

Collaborating to advance DSA adoption

The semiconductor industry has extensive experience with lithography, but DSA requires a shift in mindset. BCP materials are not something that the industry is used to, and revolutionary rather than evolutionary changes in materials and processes can face resistance. DSA needs to be demonstrated on real devices before it can achieve traction in the semiconductor market.

Collaborative efforts between semiconductor industry materials suppliers and chemical companies with deep experience in BCPs are one route to bridge this gap. One such collaboration is currently underway. Brewer Science has teamed up with Arkema, a company with two decades of experience producing BCPs, but little leverage with the semiconductor industry. The partnership, begun in 2015, has led to pilot production of DSA materials, paving the way for the technique to move out of the laboratory and into commercial semiconductor products.

DSA and EUV should be envisioned as complementary, not competing, techniques that will eventually become mainstream for fine-pitch lithography at the N7 node and beyond. Partnerships between materials and chemical companies are poised to enable this transition, unlike previous efforts by single organizations.

The basics of laser marking are reviewed, as well as current and emerging laser technologies.

BY DIETRICH TÖNNIES, Ph.D. and DIRK MÜLLER, Ph.D., Coherent Inc., Santa Clara, CA

Laser marking is established at multiple points in semiconductor production and applications continue to diversify. There are several laser technologies servicing the application space. This article reviews the basics of laser marking and the current and emerging laser technologies they utilize. It is intended to give a clear sense of what applications parameters drive the choice of laser (speed, cost, resolution, etc.), and provide those developing a new application some guidance on how to select the optimum technology.

Laser marking basics

Laser marking usually entails inducing a visible color or texture change on a surface. Alternatively, although less commonly, marking sometimes involves producing a macroscopic change in surface relief (e.g.engraving). To understand what laser type is best for a specific marking application, it is useful to examine the different laser/ material interactions that are generated by commonly used laser types.

Most frequently, lasers produce high contrast marks through a thermal interaction with the work piece. That is, material is heated until it undergoes a chemical reaction (e.g. oxidation) or change of crystalline structure that produces the desired color or texture change. However, the particulars of this process vary significantly between different materials and laser types.

CO2 lasers have been employed extensively for PCB marking because they provide a fast method of producing high contrast features. However, they are rarely selected when marking at the die or package level. This is because the focused spot size scales with wavelength due to diffraction. CO2 lasers emit the longest infrared (IR) output of any marking laser. Additionally, IR penetrates far into many materials, which can cause a substantial thermal impact on surrounding structures. Consequently, CO2 laser marking is limited to producing relatively large features where a significant heat affected zone (HAZ) can be tolerated.

Fiber lasers, which offer high power output in the near IR, have emerged over the past few years as one of the most cost effective tools for high-speed marking. Furthermore, the internal construction of fiber lasers renders a compact footprint, facilitating their integration into marking and test handlers. Cost and space savings are further enhanced when the output of a single, high power fiber laser is split, feeding two scanner systems.

Screen Shot 2017-09-22 at 12.00.12 PM

But fiber lasers have disadvantages, too. One reason for the low cost of many fiber lasers is that they are produced in high volumes with designs meant for general-purpose applications. For example, they usually produce a high quality beam with a Gaussian intensity profile. This is advantageous for many material processing applications, but not always for laser marking. In fact, a more uniform beam intensity distribution, called a flat-top profile, is sometimes more useful since it produces marks with a sharper, more abrupt edge (rather than a smooth transition from the marked to the unmarked region). Coherent recently introduced a new type of fiber (NuBEAM Flat-Top fiber technology) which enables efficient conversion of single-mode laser beams into flat-top beam profiles, specifically to address this issue.

Other quality criteria, such as high-purity linear polarization, and stability of pulse energy and pulse width, are difficult to achieve with low-cost fiber lasers. This limits their use in more stringent or sensitive marking applications. From a practical standpoint, most fiber lasers cannot be repaired in the field, but are replaced as a whole. This leads to longer equipment downtime and increased maintenance efforts as compared to traditional marking lasers based on diode-pumped, solid-state (DPSS) technology (specifically, DPSS is used here to refer to lasers with crystal resonators).

DPSS lasers also emit in the near infrared. Generally, these lasers are more expensive than a fiber laser of the same output power level. So, infrared DPSS lasers are most commonly used in applications having technical requirements that cannot be met by fiber lasers,such as high volume production of more advanced and expensive semiconductor devices.

Screen Shot 2017-09-22 at 12.00.21 PM Screen Shot 2017-09-22 at 12.00.29 PM

One advantage of DPSS laser technology is that it can be configured to directly produce a multi-mode beam profile which is essentially flat-top. The Coherent ❘ Rofin PowerLine E Air 30-1064 IC is an example which has found extensive use in semiconductor marking, since it provides an efficient way to rapidly produce very high contrast marks.

Another useful feature of DPSS lasers, which produce pulsewidths in the nanosecond regime, is that their output is much more stable than that of fiber lasers. This makes it much easier to reliably frequency double or triple their infrared light within the laser head, giving a choice of output in the green or ultraviolet (UV). Output at these wavelengths provides two significant benefits. First, they offer additional options in matching the absorption of the material to the laser wavelength. Stronger absorption generally yields higher marking efficiency and reduced HAZ, since the laser light doesn’t penetrate as far into the material. The second benefit of shorter wavelengths is the ability to focus to smaller spot sizes (because of their lower diffraction) and produce smaller, finer marks.

However, frequency multiplied DPSS lasers are generally more costly and voluminous than either fiber lasers or infrared DPSS lasers with comparable output power. Lower power translates into reduced marking speed.

Therefore, green and UV DPSS lasers are typically employed when they offer a significant advantage due to the particular absorption characteristics of the material(s) being marked.

Another emerging and important class of marking lasers has pulsewidths in the sub-nanosecond range. Due to the nature of the laser/material interaction at short pulsewidths, these lasers tend to produce the smallest possible HAZ with excellent depth control.

There are just a few products currently on the market that exploit this property. One example is the PowerLine Pico 10 from Coherent ❘ Rofin which generates 0.5 ns laser pulses in either the near IR (8 W total power) or green (3 W total power), at pulse repetition rates between 300 kHz and 800 kHz. This combination of output characteristics makes it capable of high speed marking of a wide range of materials where mark penetration depth must neces- sarily be shallow because of low material thickness, or to minimize HAZ.

Laser marking today

Typically, the first consideration in choosing a laser for a specific application is matching the absorption characteristics of the material with the laser wavelength. Similarly, desired feature size is also driven by laser wavelength, as well as by the precision of the beam scanning system. Next, HAZ constraints usually determine the maximum pulsewidth which can be used (although this choice is again highly material dependent). To see how these parameters interact in practice, it’s useful to review some real world applications.

Screen Shot 2017-09-22 at 12.00.37 PM

Epoxy-based molding compounds

The most commonly used molding compounds absorb very well in the near IR. Specifically, the near IR laser transforms the usually black molding compound into a gray/white powder, yielding high contrast marks. Plus, many IC packages have mold compound caps thick enough to easily tolerate a marking depth of 30 μm to 50 μm. As a result, many marking systems based on near IR lasers, both fiber and DPSS, are currently in use.

However, some semiconductor devices with small form factor have only thin mold compound caps to protect wire bonded silicon dies, and a marking depth of only 10 μm or less is required. Increasingly, green lasers are used for this type of shallow marking because of a stronger absorption at this wavelength by the epoxy matrix.

Ceramics

The process window when marking ceramics, such as used in packaging power semiconductors, high-brightness LEDs, RF devices, saw filters or MEMS sensors, is relatively narrow. Accurate focus and high pulse energy are critical to ensure reliable marking results, and ideally, the laser marker should have the capability to adjust the focus of the laser beam onto the ceramic surface in real time, in order to compensate for package height variations. Because of their more reliable interaction with ceramic materials, DPSS lasers based on Nd:YAG, which offer high pulse energies and relatively long pulses, are often still used for marking ceramic lids and substrates. Coherent ❘ Rofin has also developed a special fiber laser (the PowerLine F 20 Varia IC), which offers adjustable pulse widths up to 200 ns, specifically to improve process windows for marking applications of this type.

The ceramic substrates used with high-power LEDs often require tiny marks to identify individual devices. IR lasers are the preferred lasers for marking these ceramic substrates, providing their spot size is not too big for the layout to be marked. For very small marking features a green laser or UV laser is often required.

Screen Shot 2017-09-22 at 12.00.57 PM Screen Shot 2017-09-22 at 12.01.04 PM

Organic substrates

IC substrates or interposers are marked during production with traceable data matrix codes. The thin green solder resist layer on top of the substrate has to carry the mark, and care has to be taken that the copper underneath the solder resist is not exposed. Moreover, data matrix codes can be quite small, with cell sizes of only 125 μm or even less. Since the spot size of the focused laser beam must thus be much smaller than the cell size, the final spot diameter must be significantly less than 100 μm.

Defective IC substrates often are identified by marking large features (e.g., a cross) into the solder resist layer. Although the part is defective, the properties of the mark are still important. This is because it has to be reliably recognized by subsequent processing tools, and also, because any delamination of the solder resist layer might cause problems during succeeding processes.

IC strips have gold pads along their periphery which are used to identify parts found to be defective after die attach and wire bonding. For defective parts, the gold pad is marked by converting its color from gold to black or to dark grey.

Ideally, it is desirable to have one laser marker that can accomplish all three of these marking applications tasks. The green DPSS laser has become the standard laser marker for these applications, with UV lasers occasionally employed for high-end substrates.

Semiconductors

The growing demand for flip-chip devices, wafer-level packaging and defective die identification drives the need for direct marking of silicon, GaAs, GaN/sapphire or other semiconductors. Silicon is partially trans- parent in the near IR, and lasers at this wavelength are used whenever deep marks into silicon are required, such as placing wafer IDs near the wafer edge. Near IR laser markers are also selected for marking molded fan-out wafer level packaging wafers.

However, for marking either flip-chips or the backside of wafers, green lasers are preferred because of the strong absorption of this wavelength in silicon. Wafer backside marking requires only very shallow marks and the shallow laser penetration avoids potential damage to the circuitry on the reverse side of the flip-chip or wafer. The need for shallow marking also minimizes the laser power requirement. For example, Coherent ❘ Rofin provides a 6 W green laser (the PowerLine E 12 SHG IC) that is well suited for wafer backside marking, and can also mark the wafer through the tape whenever the wafer is mounted on a film frame.

Metals

Near IR lasers are widely used for marking the metal lids used with microprocessors and other high power consumption ICs.

Leadframes, which are plated with tin, silver or gold, are marked either before or after plating. Since leadframes are used for cost sensitive devices, capital investment is critical, and economical fiber lasers are often chosen for this reason.

Laser marking tomorrow

As packages get thinner and smaller, they will require shallower, higher resolution marks. Sub-nanosecond lasers are the most promising method for producing these types of marks, and are compatible with a wide range of materials. The diverse capabilities of this technology are shown in Figure 5, which depicts marking results on four different materials using a sub-nanosecond laser (Coherent ❘ Rofin PowerLine Pico 10-532 IC).

The first image is a flexible IC substrate; very thin solder resist layers and metal coatings make it important that the laser does not cause delamination. Here, the circular gold pad has been converted to black without delamination. In the next image, an IC substrate has been given a white mark, again without delaminating the solder resist.

The third image shows very small characters (< 150 μm) marked on the backside of a silicon wafer containing hundred thousands of tiny discrete semiconductor devices. Producing marks of this resolution through the film would be difficult to accomplish with a nanosecond pulsewidth laser.

The final image is a copper leadframe coated with thin silver film. Here, the goal is to produce a shallow mark with high contrast without engraving the under- lying material, which has been accomplished with the sub-nanosecond laser.

Conclusion

Semiconductor fabrication and packaging represent challenging marking applications, often requiring small, fine marks produced without a significant effect on surrounding material. An overall trend towards smaller and thinner device geometries will drive increased use of higher precision laser tools, such as those utilizing green and UV nanosecond lasers, and even sub-nanosecond lasers, while cost-sensitive applications will continue to utilize inexpensive fiber lasers.

Applied Materials, Inc. will explore the future of computing in the era of artificial intelligence (A.I.) at its 2017 Analyst Day on Wednesday, September 27 in New York. In his presentation, Applied president and CEO Gary Dickerson will explain how the rapid increase in data generation, combined with A.I. and machine learning, creates the need for new system architectures and compute models in the years ahead.

“The move to artificial intelligence signals a new era for computing that is driving major changes to the way logic and memory chips are designed and manufactured,” said Gary Dickerson. “New materials and innovative chip architectures will increasingly be needed to bring faster processors and more efficient memory to market, and Applied Materials is at the foundation with the solutions that enable the A.I. revolution.”

Applied will also host a panel of technical experts for a discussion titled “Enabling the A.I. Era.” The panelists include:

  • Christos Georgiopoulos, Former Vice President at Intel Corporation and Professor of High Energy Physics at Florida State University and CERN
  • Matt Johnson, Senior Vice President and General Manager in Automotive, NXP Semiconductors
  • Mukesh Khare, Vice President of Semiconductor Research, IBM Research
  • Praful Krishna, CEO, Coseer
  • Jay Kerley, Group Vice President and CIO, Applied Materials

Applied Materials’ Analyst Day presentations will be webcast live beginning at 1:00 p.m. EDT (10:00 a.m. PDT) on the company’s investor relations website: http://www.appliedmaterials.com/company/investor-relations.

North America-based manufacturers of semiconductor equipment posted $2.18 billion in billings worldwide in August 2017 (three-month average basis), according to the August Equipment Market Data Subscription (EMDS) Billings Report published today by SEMI.

SEMI reports that the three-month average of worldwide billings of North American equipment manufacturers in August 2017 was $2.18 billion.The billings figure is 3.9 percent lower than the final July 2017 level of $2.27 billion, and is 27.7 percent higher than the August 2016 billings level of $1.71 billion.

“Equipment billings in August declined relative to July, signaling a pause in this year’s extraordinary growth,” said Ajit Manocha, president and CEO of SEMI. “Nonetheless monthly billings remain well above last year’s monthly levels.”

The SEMI Billings report uses three-month moving averages of worldwide billings for North American-based semiconductor equipment manufacturers. Billings figures are in millions of U.S. dollars.
Billings
(3-mo. avg)
Year-Over-Year
March 2017
$2,079.7
73.7%
April 2017
$2,136.4
46.3%
May 2017
$2,270.5
41.8%
June 2017
$2,300.3
34.1%
July 2017 (final)
$2,269.7
32.9%
August 2017 (prelim)
$2,181.8
27.7%

Source: SEMI (www.semi.org), September 2017

Synopsys, Inc. (Nasdaq: SNPS) today announced that GLOBALFOUNDRIES (GF) has certified the Synopsys Design Platform for the GF 22nm FD-SOI (22FDX) process, ensuring designers achieve optimized implementation and predictable signoff results using industry leading digital design tools. This certification leveraged the silicon-proven GF Foundry Reference Flow for the Synopsys Design Platform, architected to realize the full potential of GF’s 22FDX process. IEEE 1801 (UPF)-driven bias voltage support throughout the flow enables optimal power and performance tradeoff during design implementation.

“GF worked closely with Synopsys to complete the rigorous certification process of the Synopsys Design Platform on our 22FDX process platform,” said Jai Durgam, vice president, Customer Design Enablement at GLOBALFOUNDRIES. “The Synopsys tools support 22FDX capabilities such as voltage dependent spacing rules, continuous-diffusion aware placement and optimal bias tap cell insertion in IC Compiler II. Having a reference flow with certified tools enables our mutual customers to take advantage of the technology differentiation, which offers FinFET-like performance and energy efficiency at a cost comparable to 28-nm planar technologies.”

Key tools and features of the Synopsys Design Platform certified for the 22FDX process include:

  • IC Compiler™ II layout with physical implementation support for non-uniform library floorplanning, implant-aware placement, multi-rail routing, and advanced power mesh creation
  • IC Validator physical signoff tool for In-Design verification, enabling early and accurate timing-aware metal fill with support for high performance DRC- and LVS-aware short finder
  • StarRC™  parasitic extraction for multi-rail signoff with support for multi-valued standard parasitic exchange format (SPEF)
  • PrimeTime® timing analysis and signoff including DMSA static timing and noise analysis, using AOCV and POCV technology

“Our broad collaboration with GLOBALFOUNDRIES has been focused on delivering the platform and IP needed for seamless adoption of the FD-SOI technology at 22 nanometers and smaller geometries,” said Michael Jackson, corporate vice president of marketing and business development for Synopsys’ Design Group. “Together, Synopsys’ full ecosystem solution and GLOBALFOUNDRIES’ FDX technology are enabling designers to take advantage of the performance and power benefits offered by this process.”

To certify their process platform with a real-world complex hierarchical design that requires the best performance in the smallest possible area and power budget, GF selected the DesignWare® EV61 Embedded Vision Processor with a convolutional neural network (CNN) engine configured for 880 MACs. DesignWare EV6x Vision Processor IP is a family of fully programmable and configurable vision processors that integrates scalar, vector DSP and CNN processing units for highly accurate and fast vision processing. Supported by a comprehensive software programing environment including the ARC® MetaWare EV Toolkit, the EV6x Vision Processors offer SoC designers a flexible, power-efficient embedded vision solution for a wide range of automotive, industrial and consumer applications.

Over the past half-century, scientists have shaved silicon films down to just a wisp of atoms in pursuit of smaller, faster electronics. For the next set of breakthroughs, though, they’ll need novel ways to build even tinier and more powerful devices.

A study led by UChicago researchers, published Sept. 20 in Nature, describes an innovative method to make stacks of semiconductors just a few atoms thick. The technique offers scientists and engineers a simple, cost-effective method to make thin, uniform layers of these materials, which could expand capabilities for devices from solar cells to cell phones.

Stacking thin layers of materials offers a range of possibilities for making electronic devices with unique properties. But manufacturing such films is a delicate process, with little room for error.

“The scale of the problem we’re looking at is, imagine trying to lay down a flat sheet of plastic wrap the size of Chicago without getting any air bubbles in it,” said Jiwoong Park, a UChicago professor with the Department of Chemistry, the Institute for Molecular Engineering and the James Franck Institute, who led the study. “When the material itself is just atoms thick, every little stray atom is a problem.”

Today, these layers are “grown” instead of stacking them on top of one another. But that means the bottom layers have to be subjected to harsh growth conditions such as high temperatures while the new ones are added — a process that limits the materials with which to make them.

Park’s team instead made the films individually. Then they put them into a vacuum, peeled them off and stuck them to one another, like Post-It notes. This allowed the scientists to make films that were connected with weak bonds instead of stronger covalent bonds–interfering less with the perfect surfaces between the layers.

“The films, vertically controlled at the atomic-level, are exceptionally high-quality over entire wafers,” said Kibum Kang, a postdoctoral associate who was the first author of the study.

Kan-Heng Lee, a graduate student and co-first author of the study, then tested the films’ electrical properties by making them into devices and showed that their functions can be designed on the atomic scale, which could allow them to serve as the essential ingredient for future computer chips.

The method opens up a myriad of possibilities for such films. They can be made on top of water or plastics; they can be made to detach by dipping them into water; and they can be carved or patterned with an ion beam. Researchers are exploring the full range of what can be done with the method, which they said is simple and cost-effective.

“We expect this new method to accelerate the discovery of novel materials, as well as enabling large-scale manufacturing,” Park said.

A research group consisting of scientists from Tomsk Polytechnic University, Germany and Venezuela proved vulnerability of a two-dimensional semiconductor gallium selenide in air. This discovery will allow manufacturing superconducting nanoelectronics based on gallium selenide, which has never been previously achieved by any research team in the world.

The study was published in Semiconductor Science and Technology.

One of the promising areas of modern materials science is the study of two-dimensional (2D) materials, i.e. thin films consisting of one or several atomic layers. 2D materials due to their electrical superconductivity and strength could be a basis for modern nanoelectronics. Optic applications in nanoelectronics require advanced materials capable of ‘generating’ great electron fluxes upon light irradiation. Gallium selenide (GaSe) is one of the 2D semiconductors that can cope with this problem most efficiently.

‘Some research teams abroad tried to create electronic devices based on GaSe. However, despite extensive theoretical studies of this material, which were published in major scientific journals, the stability of the material in real devices remained unclear,’ says Prof. Raul Rodriguez, the Department of Lasers and Lighting Engineering.

The research team revealed the reasons behind this. They studied GaSe by means of Raman spectroscopy and x-ray photoelectron spectroscopy that allowed proving the existence of chemical bonds between gallium and oxygen. Photoluminescence in oxidized substance is absent that also proves the formation of oxides. It means that the scientists revealed that GaSe oxidizes quickly in air and loses its electrical conductivity necessary for creating nanoeletronic devices.

‘GaSe monolayers become oxidized almost immediately after being exposed to air. Further research of GASe stability in air will allow making proposals how to protect it and maintain its optoelectronic properties,’ emphasize the authors.

According to Prof. Rodriguez, for GaSe not to lose its unique properties it should be placed in a vacuum or inert environment. For example, it can be applied in encapsulated devices that are vacuum-manufactured and then covered with a protective layer eliminating air penetration.

This method can be used to produce next generation optoelectronics, detectors, light sources and solar batteries. Such devices of ultra-small sizes will have very high quantum efficiency, i.e. they will be able to generate large electron fluxes under small external exposure.