Yearly Archives: 2017

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that it has received three TSMC Partner of the Year awards at this year’s TSMC Open Innovation Platform (OIP) Ecosystem Forum. Cadence was presented with awards for the joint development of the 7nm FinFET Plus design infrastructure and the 12nm FinFET Compact (12FFC) design infrastructure and the joint delivery of the automotive design enablement platform.

The awards for the joint development of the 7nm FinFET Plus design infrastructure and 12FFC design infrastructure were awarded based on the early, in-depth collaboration between TSMC and Cadence on FinFET technology enablement and the development of the latest advanced-node solutions for next-generation system-on-chip (SoC) designs. Cadence secured the award for the joint delivery of the automotive design enablement platform based on collaboration and support of aging simulation and advanced electromagnetic (EM) rules for the 16FFC process.

“Cadence continues to partner with TSMC to deliver the innovation and deep technical expertise that is required to address evolving requirements for the latest process nodes, such as 7nm FinFET Plus and 12FFC, and within growth industries, such as automotive,” said Dr. Anirudh Devgan, executive vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “These awards from TSMC highlight Cadence’s dedication to delivering the innovative tools that our customers need for advanced SoC and automotive designs.”

“Throughout the history of our long, collaborative relationship with Cadence, they have consistently delivered high-quality results and continue to invest in the most advanced technologies as demonstrated by the latest developments in 7nm FinFET Plus, 12FFC and automotive design enablement,” said Suk Lee, senior director of the Design Infrastructure Marketing Division at TSMC. “The awards are indicative of our close collaboration with Cadence, and we look forward to continuing the development of advanced-node solutions for our mutual customers.”

Intel Corporation today announced that Andrew Wilson, CEO of Electronic Arts Inc., has been elected to Intel’s board of directors. Wilson’s election brings Intel’s board membership to 12.

“Andrew understands first-hand how technology and data create opportunity with his transformation of EA from offline packaged goods to a leader in online digital services,” said Intel Chairman Andy Bryant. “In addition to his experience leading and growing a global, technology-driven company, Andrew possesses a combination of creativity and business acumen that will further strengthen Intel’s board.”

Wilson, 43, joined Electronic Arts (“EA”) in May 2000, and has served as the company’s chief executive officer and a director of EA since September 2013. During his tenure as CEO, EA has launched groundbreaking new games and services, reached record player engagement levels across its global franchises, and transformed into one of the world’s leading digital entertainment companies. Prior to his appointment as CEO, Wilson held several leadership positions at EA, including executive vice president of EA SPORTS. He also serves as chairman of the board for the World Surf League.

GLOBALFOUNDRIES today announced the availability of a new set of enhanced RF SOI process design kits (PDKs) to help designers improve their designs of RF switches and deliver differentiated RF front-end solutions for a wide range of markets including front-end modules for mobile devices, mmWave, 5G and other high-frequency applications.

GF’s advanced RF technology platform, 7SW SOI, is optimized for multi-band RF switching in next-generation smartphones and poised to drive innovation in Internet of Things (IoT) applications. Designed for use with Coupling Wave Solutions’ (CWS) simulation tool, SiPEX™, GF’s 7SW SOI PDK allows designers to integrate RF switches with other critical RF blocks that are essential to the design of complex electronic systems for future RF communication chips. Specifically, this new capability allows designers to improve RF simulation output by simulating a highly-resistive substrate parasitic effect across their entire design.

“GF leads the industry in RFSOI technology, and we are committed to providing our customers with design productivity solutions for our RF processes,” said Bami Bastani, senior vice president of RF at GF. “CWS’ SiPEX™ tool provides our customers with best-in-class correlation between simulated results and real world measurements, further optimizing the design layout to achieve efficiency and deliver differentiated RF front-end solutions.”

“This is great news for the RF design community,” said Brieuc Turluche, chairman of the board of directors and chief executive officer of CWS. “The integration of SiPEX into GF’s RF SOI PDKs is a major milestone to achieve first-time correct complex and optimized RF SOI designs for high-performing cellular, IoT, 5G and Wi-Fi communication chips.”

GF’s RF SOI technologies offer significant performance, integration and area advantages in front-end RF solutions for mobile devices and RF chips for high-frequency, high-bandwidth wireless infrastructure applications. CWS’ SiPEX accelerates the design of RF SOI switches by improving linearity simulation accuracy. It can also be effective in the design of low-noise amplifiers (LNA) and power amplifiers (PA), enabling designers to reduce their size to lower costs.

SiPEX™ is available in the current release of GF’s 7SW SOI PDK. For more information on the company’s RF SOI solutions, contact your GF sales representative or go to www.globalfoundries.com.

Decades ago, the Moore’s law predicted that the number of transistors in a dense integrated circuit doubles approximately every two years. This prediction was proved to be right in the past few decades, and the quest for ever smaller and more efficient semiconductor devices have been a driving force in breakthroughs in the technology.

With an enduring and increasing need for miniaturization and large-scale integration of photonic components on the silicon platform for data communication and emerging applications in mind, a group of researchers from the Hong Kong University of Science and Technology and University of California, Santa Barbara, successfully demonstrated record-small electrically pumped micro-lasers epitaxially grown on industry standard (001) silicon substrates in a recent study. A submilliamp threshold of 0.6 mA, emitting at the near-infrared (1.3?m) was achieved for a micro-laser with a radius of 5 μm. The thresholds and footprints are orders of magnitude smaller than those previously reported lasers epitaxially grown on Si.

Their findings were published in the prestigious journal Optica on August 4, 2017 (doi: 10.1364/OPTICA.4.000940).

“We demonstrated the smallest current injection QD lasers directly grown on industry-standard (001) silicon with low power consumption and high temperature stability,” said Kei May Lau, Fang Professor of Engineering and Chair Professor of the Department of Electronic & Computer Engineering at HKUST.

“The realization of high-performance micron-sized lasers directly grown on Si represents a major step toward utilization of direct III-V/Si epitaxy as an alternate option to wafer-bonding techniques as on-chip silicon light sources with dense integration and low power consumption.”

The two groups have been collaborating and has previously developed continuous-wave (CW) optically-pumped micro-lasers operating at room temperature that were epitaxially grown on silicon with no germanium buffer layer or substrate miscut. This time, they demonstrated record-small electrically pumped QD lasers epitaxially grown on silicon. “Electrical injection of micro-lasers is a much more challenging and daunting task: first, electrode metallization is limited by the micro size cavity, which may increase the device resistance and thermal impedance; second, the whispering gallery mode (WGM) is sensitive to any process imperfection, which may increase the optical loss,” said Yating Wan, a HKUST PhD graduate and now postdoctoral fellow at the Optoelectronics Research Group of UCSB.

“As a promising integration platform, silicon photonics need on-chip laser sources that dramatically improve capability, while trimming size and power dissipation in a cost-effective way for volume manufacturability. The realization of high-performance micron-sized lasers directly grown on Si represents a major step toward utilization of direct III-V/Si epitaxy as an alternate option to wafer-bonding techniques,” said John Bowers, Deputy Chief Executive Officer of AIM Photonics.

Modern life will be almost unthinkable without transistors. They are the ubiquitous building blocks of all electronic devices: each computer chip contains billions of them. However, as the chips become smaller and smaller, the current 3D field-electronic transistors (FETs) are reaching their efficiency limit. A research team at the Center for Artificial Low Dimensional Electronic Systems, within the Institute for Basic Science (IBS), has developed the first 2D electronic circuit (FET) made of a single material. Published on Nature Nanotechnology, this study shows a new method to make metal and semiconductor from the same material in order to manifacture 2D FETs.

In simple terms, FETs can be thought as high-speed switches, comprised of two metal electrodes and a semiconducting channel in between. Electrons (or holes) move from the source electrode to the drain electrode, flowing through the channel. While 3D FETs have been scaled down to nanoscale dimensions successfully, their physical limitations are starting to emerge. Short semiconductor channel lengths lead to a decrease in performance: some electrons (or holes) are able to flow between the electrodes even when they should not, causing heat and efficiency reduction. To overcome this performance degradation, transistor channels have to be made with nanometer-scale thin materials. However, even thin 3D materials are not good enough, as unpaired electrons, part of the so-called “dangling bonds” at the surface interfere with the flowing electrons, leading to scattering.

Passing from thin 3D FETs to 2D FETs can overcome these problems and bring in new attractive properties. “FETs made from 2D semiconductors are free from short-channel effects because all electrons are confined in naturally atomically thin channels, free of dangling bonds at the surface,” explains Ji Ho Sung, first author of the study. Moreover, single- and few-layer form of layered 2D materials have a wide range of electrical and tunable optical properties, atomic-scale thickness, mechanical flexibility and large bandgaps (1~2 eV).

The major issue for 2D FET transistors is the existence of a large contact resistance at the interface between the 2D semiconductor and any bulk metal. To address this, the team devised a new technique to produce 2D transistors with semiconductor and metal made of the same chemical compound, molybdenum telluride (MoTe2). It is a polymorphic material, meaning that it can be used both as metal and as semiconductor. Contact resistance at the interface between the semiconductor and metallic MoTe2 is shown to be very low. Barrier height was lowered by a factor of 7, from 150meV to 22meV.

IBS scientists used the chemical vapor deposition (CVD) technique to build high quality metallic or semiconducting MoTe2 crystals. The polymorphism is controlled by the temperature inside a hot-walled quartz-tube furnace filled with NaCl vapor: 710°C to obtain metal and 670°C for a semiconductor.

The scientists also manufactured larger scale structures using stripes of tungsten diselenide (WSe2) alternated with tungsten ditelluride (WTe2). They first created a thin layer of semiconducting WSe2 with chemical vapor deposition, then scraped out some stripes and grew metallic WTe2 on its place.

It is anticipated that in the future, it would be possible to realize an even smaller contact resistance, reaching the theoretical quantum limit, which is regarded as a major issue in the study of 2D materials, including graphene and other transition metal dichalcogenide materials.

The International Microelectronics And Packaging Society (IMAPS) will celebrate the 50th anniversary of its flagship technical conference – the IMAPS Symposium – from October 9 – 12, 2017, as microelectronics engineers and scientists gather at the Raleigh Convention Center near Research Triangle Park, North Carolina, USA to take part in the electronics industry’s largest technical conference dedicated to advanced microelectronics packaging technology. Researchers and exhibitors will showcase their work during a comprehensive conference program of technical papers, panels, special sessions, short courses/tutorials, and an exhibition that will spotlight premier work in the fields of microelectronics, semiconductor packaging and circuit design.

The 50th International Symposium on Microelectronics is an international technology forum for the presentation of applied research on microelectronics, consisting of more than 180 papers presented by researchers from corporations, universities and government labs worldwide, with five technical tracks: Chip Packaging Interactions; High Performance, Reliability, & Security; Advanced Packaging & Enabling Technologies; Advanced Packaging & System Integration; and Advanced Materials & Processes.

Keynote Presentations Lead Off the IMAPS Technical Program on Tuesday, October 10
Four keynote addresses from leading industry experts include:

“Packaging Challenges for the Next Generation of Mobile Devices,” by Ahmer Syed, Senior director of package engineering, Qualcomm Technologies

“Packaging without the Package – A More Holistic Moore’s Law,” by Subramanian (Subu) S. Iyer, distinguished chancellor’s professor in the Charles P. Reames Endowed Chair of the Electrical Engineering Department at the University of California at Los Angeles (UCLA) and Director of the Center for Heterogeneous Integration and Performance Scaling (CHIPS)

“Electronics Outside the Box: Building a Manufacturing Ecosystem for Flexible Hybrid Electronics,” by Benjamin Leever, senior materials engineer, Air Force Research Laboratory (AFRL) Soft Matter Materials Branch

“Transforming Electronic Interconnect,” by Tim Olson, founder & CTO, Deca Technologies

International Panel Session & Wine Reception on Wednesday, October 11
A panel session on “Global Perspectives on Packaging Requirements & Trends Towards 2025” will be moderated by Jan Vardaman, TechSearch International and Gabriel Pares, CEA-Leti. Panelist will include representatives from Asia (Yasumitsu Orii, NAGASE Group and Ton Schless, SIBCO), Europe (Steffen Kroehnert, Nanium and Eric Bridot, SAFRAN), and North America (David Jandzinski, Qorvo). The 90-minute panel session includes a wine reception.

Diversity Roundtable & Networking Discussions on Monday, October 9
Following the opening reception, IMAPS leaders will conduct a series of roundtable discussions designed to inspire conversations about overcoming diversity barriers, the strengths inherent in a diverse workforce, identifying and collaborating with a mentor, and more.

Posters & Pizza Session on Thursday, October 12
One of the fastest-growing segments of the IMAPS conference is the popular “Posters & Pizza” session held outside the exhibit hall, giving attendees the opportunity to interact one-on-one with presenters in a more informal setting.

Professional Development Courses (Short Courses & Tutorials) on Monday, October 9
Preceding the IMAPS Symposium technical program is a full day of professional development opportunities, presented as a series of 2-hour sessions in four tracks: Intro to Microelectronics Packaging; Next Generation Packaging Challenges; Baseline & Emerging Technologies; and Reliability. These short courses represent a unique opportunity, only available through IMAPS, for participants to personally interact with the instructors, and with each other in small groups from 10 – 30 people, led by industry experts in the field with ample time for questions and networking.

Student Opportunities at IMAPS
As part of its ongoing mission IMAPS invites students to participate in an informal networking event on Tuesday, October 10 with IMAPS industry leaders over lunch in the exhibit hall, giving them an chance to learn about career opportunities, navigating the hiring process, and other topics. In addition, the IMAPS Microelectronics Foundation sponsors a student paper competitionin conjunction with the Symposium that awards more than $3,500 in scholarships for outstanding student papers.

Social Events & an Introduction to the RTP/Raleigh Area’s Technology Community
In addition to the technical program, a variety of social events are planned around the IMAPS Symposia, including the Annual David C. Virissimo Memorial Fall Golf Classic, a charity golf outing scheduled for Monday, October 9 at NCSU’s Lonnie Poole Golf Course. Proceeds from the event benefit the IMAPS Microelectronics Foundation.

Monday evening’s welcome reception will feature NC-themed entertainment from a local bluegrass band, and participants will also be able to view historical photos and other memorabilia spanning 50 years of IMAPS history.

There is also a scheduled tour of the nearby Micross Advanced Interconnect Technology (AIT) facility, one of the premier wafer bumping and wafer level packaging facilities in the U.S., with more than 20 years experience providing leading edge interconnect and 3D integration technologies (TSV, Si interposers, 3D IC) to worldwide customers.

New to the Symposium this year is a unique opportunity for IMAPS attendees to experience the vibrant technology community in the greater RTP/Raleigh area. IMAPS has invited local non-profit organizations that comprise the area’s rapidly-growing technology ecosystem to participate in a special area adjacent to the exhibit hall during the day of October 10, providing an opportunity for IMAPS Symposium attendees to network and interact.

To register for the IMAPS 50th International Symposium on Microelectronics, please visit the online registration site for more information, or contact Brianne Lamm, IMAPS Marketing & Events Manager, at [email protected] or 980-299-9873.

The large thin film transistor (TFT) display market is expected to continue to expand in 2017 despite slower end-market demand, according to IHS Markit (Nasdaq: INFO).

While unit shipments are expected to be up 1 percent in 2017 to 688 million units, compared to the previous year, area shipment forecasts show growth of 6 percent in the same period, to 180 million square meters.

Figure 1

Among displays of 9 inches or larger, tablet PC displays are on track to record the highest year-on-year growth in unit shipments in 2017, with 10 percent growth to 93 million units. “It is because first-tier set brands are increasing the number of tablet PC models with larger screens. The new 10.5-inch iPad pro is a good example,” said Peter Su, principal analyst at IHS Markit.

The second fastest-growing application is notebook PC displays, with a 4 percent year-on-year growth to about 175 million units. “Chinese panel makers are aggressively trying to expand in this market, while first-tier panel makers are actually retreating panel production,” Su said.

On the flip side, TV displays are showing a contraction in 2017 by 3 percent year on year, dropping to 257 million units due to slower end-market demand. “Prices of large displays, particularly TV panels, have stayed high for almost a year. TV brands started revising down their business plan, cutting their panel purchases,” Su said.

In terms of area shipments, however, large displays for all applications are forecast to see growth in 2017 as larger screens become more popular with consumers. TV display accounts for 78 percent of total large display shipments by area, and is expected to see a 5 percent growth in 2017.

“First-tier panel makers, especially South Korean companies, already started shifting their production to larger sizes — 49 inches or larger — while reducing production of smaller panels, with lower profitability, to achieve better financial performance,” Su said. “Chinese panel makers are following suit and started increasing production of larger TV displays to 43-inch or larger.”

For a panel manufacturer’s perspective, preparing for potential oversupply in the near future is another reason behind the TV size migration. New fabs are under construction in China, including 10.5 generation, and could increase supply significantly.  “One way for panel makers to overcome the oversupply is to increase area consumption via size migration,” Su said.

LG Display is expected to continue accounting for the largest market share in 2017 with 21 percent as measured by unit shipments. BOE, a Chinese display maker that has been increasing its shipments significantly, is forecast to take 20.7 percent, up 2 percentage points from 2016, gaining on LG Display.

Figure 2

Entegris Inc. (NASDAQ: ENTG), a specialty materials provider, announced at SEMICON Taiwan today the availability of its Oktolex membrane technology for advanced point-of-use photolithography applications. Oktolex’s membranes remove critical photochemical contaminants by enhancing the native retention mechanisms of each membrane type to match the needs of each chemistry. By matching membrane characteristics with specific contaminant-adsorption mechanisms, Oktolex membranes further optimize removal performance with no adverse interactions with the chemical composition.

“Breaking from convention, we’ve developed a cleaner, faster, and more effective way to remove the most challenging contaminants with a tailored approach to the specific contamination control needs of ArF, KrF, and EUV applications for Logic, DRAM, and 3D NAND devices,” noted Entegris Senior Vice President and General Manager of Microcontamination Control, Clint Haris. “The true advantage of this technology is its ability to create membranes that effectively remove the targeted contaminants, while not altering the chemical composition. This combination enables us to collaborate with customers to create precise contaminant removal solutions that meet the needs of advanced nodes and reduce tool downtime.”

Oktolex technology is currently available in Entegris Impact 8G point-of-use photochemical filters.

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that John Wall, corporate vice president of finance and corporate controller of Cadence, has been appointed senior vice president and chief financial officer of Cadence, effective October 1, 2017. Geoff Ribar, current CFO of Cadence, will remain with the company as a senior advisor until his previously announced retirement at the end of March 2018.

Mr. Wall, a 20-year Cadence executive, has been corporate controller for the past year-and-a-half, during which he has worked closely with Mr. Ribar to set and execute the company’s financial goals. He previously served as vice president of finance, where he was responsible for worldwide revenue accounting and sales finance, and was instrumental in development of the ratable revenue model and sales models that Cadence uses. At the beginning of his tenure with Cadence, Mr. Wall established the Cadence office in Dublin, Ireland, was European controller and implemented the company’s international tax structure.

“The Board of Directors and I are excited to appoint John Wall as the next CFO of Cadence,” said Lip-Bu Tan, president and chief executive officer of Cadence. “We are confident that John’s deep financial experience and knowledge about our business will serve us well as we build upon the important progress we have made with our System Design Enablement strategy, further expand Cadence’s position with customers and improve our financial position.”

Mr. Tan continued, “On behalf of the Board and the entire Cadence team, I want to express our deepest gratitude to Geoff Ribar for his significant contributions to Cadence’s excellent financial management over the last seven years as CFO. Geoff played a key role in building the financial foundation through which we steadily increased our operating margin and improved our performance. We look forward to continuing to benefit from his exceptional skill and leadership during the transition and wish him all the best for the future.”

Cadence has also appointed Michelle Quejado as corporate controller, reporting to Mr. Wall. Ms. Quejado was most recently interim CFO at Zynga Inc., where she also served as corporate controller and chief accounting officer. Prior to Zynga, she served in multiple financial executive positions at Lam Research Corporation, including assistant corporate controller.

Flex Logix Technologies, Inc., a supplier of embedded FPGA IP and software, today announced it has won the TSMC Open Innovation Platform’s Partner of the Year Award 2017 in the category of New IP for its EFLX embedded FPGA IP product.

“We are honored to win this prestigious award as it highlights the close alignment with TSMC that Flex Logix has achieved with its EFLX platform: EFLX embedded FPGA is available for TSMC 40nm, 28nm and 16nm process nodes with array sizes from 100 to >100K LUTs with options for DSP and any size/type of embedded RAM,” said Geoff Tate, CEO and co-founder of Flex Logix. “Flex Logix has worked closely with TSMC since the company was founded in 2014 and is proud to meet TSMC’s rigorous standards as an IP Alliance Member.”

Embedded FPGA is a new type of semiconductor IP enabling high-volume chip designers to incorporate reconfigurable logic to allow chips to be updated even in-system to adapt to new standards, new protocols, new algorithms and to customize chips for customers faster and more cost effectively than mask changes.

The award was presented during a ceremony at this year’s TSMC Open Innovation Platform Ecosystem Forum on September 13, 2017 in Santa Clara. Tate and Senior Vice President of Engineering Cheng Wang accepted the award on behalf of Flex Logix.