Yearly Archives: 2017

TowerJazz, the global specialty foundry, today announced the release of its advanced 5V 65nm power process providing customers with multiple advantages over 0.18um 5V technologies. The advanced 5V 65nm technology increases TowerJazz’s footprint in the 5V power market by offering enhanced Rdson efficiency with an attractive die cost advantage over 0.18um 5V processes. This technology is based on TowerJazz’s automotive 300mm 65nm process platform manufactured in its Uozu, Japan facility and supports both best in class quality and manufacturing cycle time.

The advanced 5V 65nm contains a rich portfolio of analog features and many different metal combinations to optimize cost/performance for any application. The first products, for several strategic customers, were already prototyped with outstanding performance. The technology is now fully released and supports Multi-layer Masking (MLM) and an MPW option to reduce engineering costs. The first MPW is targeted for November 2017.

TowerJazz’s 5V 65nm power technology offers high Rdson efficiency using tighter design rules for power devices, and a thick copper top metal for large current applications, enabling the 5V transistors using a 65nm design to achieve dense digital capabilities and a dense analog periphery, with a low number of manufacturing masks. The technology offers an average of 30% area reduction for a given 5V power transistor and typically a 35% die size reduction for a mixed-signal chip. An optimization effort to minimize cost and manufacturing layers needed to support 5V enables highly competitive solutions for many different markets such as automotive, industrial and consumer. The advanced 5V 65nm supports high current power applications such as PMIC, DC/DC converters, load switches and point of load ICs using single and dual 3.3um thick copper metal layers.

“Streamlining our feature rich automotive quality 65nm technology allows TowerJazz to provide very attractive 5V power and mixed-signal solutions with the high quality standard set required for servicing the automotive market,” said Shimon Greenberg, Vice President and General Manager of Mixed-Signal and Power Management Business Unit, TowerJazz. “This technology is utilized for relatively high current power ICs at 5V which have large growth drivers to advanced analog and mixed-signal ICs.”

Many seashells, minerals, and semiconductor nanomaterials are made up of smaller crystals, which are assembled together like the pieces of a puzzle. Now, researchers have measured the forces that cause the crystals to assemble, revealing an orchestra of competing factors that researchers might be able to control.

The work has a variety of implications in both discovery and applied science. In addition to providing insights into the formation of minerals and semiconductor nanomaterials, it might also help scientists understand soil as it expands and contracts through wetting and drying cycles. In the applied realm, researchers might use the principles to develop new materials with unique properties for energy needs.

The results, published in the Proceedings of the National Academy of Sciences in July, describe how the arrangement of the atoms in the crystals creates forces that pull them together and align them for docking. The study reveals how the attraction becomes stronger or weaker as water is heated or salt is added, both of which are common processes in the natural world.

The multinational team, led by chemists Dongsheng Li and Jaehun Chun from the Department of Energy’s Pacific Northwest National Laboratory, explored the attractive forces between two crystal particles made from mica. A flaky mineral that is commonly used in electrical insulation, this silicon-based mineral is well-studied and easy to work with because it chips off in flat pieces with nearly-perfect crystal surfaces.

Forces and faces

Crystallization often occurs through assembly of multi-faceted building blocks: some faces on these smaller crystals line up better with others, like Lego blocks do. Li and Chun have been studying a specific crystallization process called oriented attachment. Among other distinguishing characteristics, oriented attachment occurs when smaller subunits of fledgling crystals align their best matching faces before clicking together.

The process creates various nonlinear forms: nanowires with branches, lattices that look like complicated honeycombs, and tetrapods — tiny structures that look like four-armed toy jacks. The molecular forces that contribute to this self-assembly are not well understood.

Molecular forces that come into play can attract or repel the tiny crystal building blocks to or from each other. These include a variety of textbook forces such as van der Waals, hydrogen bonding, and electrostatic, among others.

To explore the forces, Li, Chun and colleagues milled flat faces on tiny slabs of mica and put them on a device that measures the attraction between two pieces. Then they measured the attraction while twisting the faces relative to each other. The experiment allowed the mica to be bathed in a liquid that includes different salts, letting them test real-world scenarios.

The difference in this work was the liquid setup. Similar experiments by other researchers have been done dry under vacuum; in this work, the liquid created conditions that better simulate how real crystals form in nature and in large industrial methods. The team performed some of these experiments at EMSL, the Environmental Molecular Sciences Laboratory, a DOE Office of Science User Facility at PNNL.

Twist and salt

One of the first things the team found was that the attraction between two pieces of mica rose and fell as the faces twisted relative to each other, like when trying to make a sandwich out of two flat refrigerator magnets (go on, try it). In fact, the attraction rose and fell every 60 degrees, corresponding with the internal architecture of the mineral, which is almost hexagonal like a honeycomb cell.

Although other researchers more than a decade ago had predicted this cyclical attraction would happen, this is the first time scientists had measured the forces. Knowing the strength of the forces is key to manipulating crystallization in a research or industrial setting.

But other things were abuzz in the mica face-off as well. Between the two surfaces, the liquid environment housed electrically charged ions from salts, normal elements found during crystallization in nature. The water and the ions formed a somewhat stable layer between the surfaces that partly kept them separated. And as they moved toward each other, the two mica surfaces paused there, balanced between molecular attraction and repulsion by water and ions.

The team also found they could manipulate the strength of that attraction by changing the type of ions, their concentration, and the temperature. Different types of ions and their concentrations changed electrostatic repulsion between the mica surfaces. The size of the ions and how many charges they carried also created more or less space within the meddling layer.

Lastly, higher temperatures increased the strength of the attraction, contrary to how temperature behaves in simpler, less complex scenarios. The researchers built a model of the competing forces that included van der Waals, electrostatic, and hydration forces.

In the future, the researchers say, the principles gleaned from this study can be applied to other materials, which would be calculated for the material of interest. For example, manipulating the attraction might allow researchers to custom-build crystals of desired sizes and shapes and with unique properties. Overall, the work provides insights into crystal growth through nanoparticle assembly in synthetic, biological, and geochemical environments.

A powdery mix of metal nanocrystals wrapped in single-layer sheets of carbon atoms, developed at the Department of Energy’s Lawrence Berkeley National Laboratory (Berkeley Lab), shows promise for safely storing hydrogen for use with fuel cells for passenger vehicles and other uses. And now, a new study provides insight into the atomic details of the crystals’ ultrathin coating and how it serves as selective shielding while enhancing their performance in hydrogen storage.

The study, led by Berkeley Lab researchers, drew upon a range of Lab expertise and capabilities to synthesize and coat the magnesium crystals, which measure only 3-4 nanometers (billionths of a meter) across; study their nanoscale chemical composition with X-rays; and develop computer simulations and supporting theories to better understand how the crystals and their carbon coating function together.

The science team’s findings could help researchers understand how similar coatings could also enhance the performance and stability of other materials that show promise for hydrogen storage applications. The research project is one of several efforts within a multi-lab R&D effort known as the Hydrogen Materials — Advanced Research Consortium (HyMARC) established as part of the Energy Materials Network by the U.S. Department of Energy’s Fuel Cell Technologies Office in the Office of Energy Efficiency and Renewable Energy.

Reduced graphene oxide (or rGO), which resembles the more famous graphene (an extended sheet of carbon, only one atom thick, arrayed in a honeycomb pattern), has nanoscale holes that permit hydrogen to pass through while keeping larger molecules at bay.

This carbon wrapping was intended to prevent the magnesium — which is used as a hydrogen storage material — from reacting with its environment, including oxygen, water vapor and carbon dioxide. Such exposures could produce a thick coating of oxidation that would prevent the incoming hydrogen from accessing the magnesium surfaces.

But the latest study suggests that an atomically thin layer of oxidation did form on the crystals during their preparation. And, even more surprisingly, this oxide layer doesn’t seem to degrade the material’s performance.

“Previously, we thought the material was very well-protected,” said Liwen Wan, a postdoctoral researcher at Berkeley Lab’s Molecular Foundry, a DOE Nanoscale Science Research Center, who served as the study’s lead author. The study was published in the Nano Letters journal. “From our detailed analysis, we saw some evidence of oxidation.”

Wan added, “Most people would suspect that the oxide layer is bad news for hydrogen storage, which it turns out may not be true in this case. Without this oxide layer, the reduced graphene oxide would have a fairly weak interaction with the magnesium, but with the oxide layer the carbon-magnesium binding seems to be stronger.

“That’s a benefit that ultimately enhances the protection provided by the carbon coating,” she noted. “There doesn’t seem to be any downside.”

David Prendergast, director of the Molecular Foundry’s Theory Facility and a participant in the study, noted that the current generation of hydrogen-fueled vehicles power their fuel cell engines using compressed hydrogen gas. “This requires bulky, heavy cylindrical tanks that limit the driving efficiency of such cars,” he said, and the nanocrystals offer one possibility for eliminating these bulky tanks by storing hydrogen within other materials.

The study also helped to show that the thin oxide layer doesn’t necessarily hinder the rate at which this material can take up hydrogen, which is important when you need to refuel quickly. This finding was also unexpected based on the conventional understanding of the blocking role oxidation typically plays in these hydrogen-storage materials.

That means the wrapped nanocrystals, in a fuel storage and supply context, would chemically absorb pumped-in hydrogen gas at a much higher density than possible in a compressed hydrogen gas fuel tank at the same pressures.

The models that Wan developed to explain the experimental data suggest that the oxidation layer that forms around the crystals is atomically thin and is stable over time, suggesting that the oxidation does not progress.

The analysis was based, in part, around experiments performed at Berkeley Lab’s Advanced Light Source (ALS), an X-ray source called a synchrotron that was earlier used to explore how the nanocrystals interact with hydrogen gas in real time.

Wan said that a key to the study was interpreting the ALS X-ray data by simulating X-ray measurements for hypothetical atomic models of the oxidized layer, and then selecting those models that best fit the data. “From that we know what the material actually looks like,” she said.

While many simulations are based around very pure materials with clean surfaces, Wan said, in this case the simulations were intended to be more representative of the real-world imperfections of the nanocrystals.

A next step, in both experiments and simulations, is to use materials that are more ideal for real-world hydrogen storage applications, Wan said, such as complex metal hydrides (hydrogen-metal compounds) that would also be wrapped in a protective sheet of graphene.

“By going to complex metal hydrides, you get intrinsically higher hydrogen storage capacity and our goal is to enable hydrogen uptake and release at reasonable temperatures and pressures,” Wan said.

Some of these complex metal hydride materials are fairly time-consuming to simulate, and the research team plans to use the supercomputers at Berkeley Lab’s National Energy Research Scientific Computing Center (NERSC) for this work.

“Now that we have a good understanding of magnesium nanocrystals, we know that we can transfer this capability to look at other materials to speed up the discovery process,” Wan said.

Lam Research Corp. (Nasdaq: LRCX), a global supplier of wafer fabrication equipment and services to the semiconductor industry, today announced it has recognized seven companies with Supplier Excellence Awards. Selected from among Lam’s extensive list of preferred global suppliers, the 2017 award winners represent partners who have demonstrated a deep commitment to collaboration and strategic operations in an evolving semiconductor industry.

“We are pleased to recognize the critical role our top suppliers play in the delivery of industry-leading products and services to our customers,” said Tim Archer, chief operating officer of Lam Research. “Lam’s business operations continue to grow—in scale, complexity, and geographic footprint. All of the suppliers recognized today demonstrate a commitment to innovation, collaboration, and partnership that will be increasingly important to our future. We are pleased to honor the achievements of these remarkable companies with our 2017 Supplier Excellence Awards.”

Award recipients were announced on September 12 at the company’s 2017 Supplier Day event, during which Lam Research focused on enhancing collaboration and renewing opportunities for mutual success with its customers and suppliers. Executives from suppliers around the world attended the event, where the following seven companies were recognized.

  • Edwards Vacuum
  • HORIBA, Ltd.
  • ILSHIN Precision Co. Ltd.
  • MKS Instruments, Inc.
  • Tokai Carbon Korea Co. Ltd.
  • TOTO, Ltd.
  • Ultra Clean Technology

SPTS Technologies, an Orbotech company and a supplier of advanced wafer processing solutions for the global semiconductor and related industries, today announced that it has been selected by Chipmore Technology Corporation Limited, an LCD driver integrated chip (IC) packaging specialist, to supply physical vapor deposition (PVD) solutions for the under bump metallization (UBM) and redistribution layers (RDL) for their flip-chip packaging line.   Chipmore chose the Sigma® fxP PVD solution for their new copper (Cu) bumping line, as it provides superior results and lowest cost of ownership over competitor systems.

“Consumer demand for high-end smartphones and other mobile devices with higher resolution screens are driving the rapid growth of advanced display driver IC’s,” stated Mr. Kevin Crofton, Corporate Vice President at Orbotech and President of SPTS Technologies. “Our Sigma fxP PVD system provides Chipmore with the most cost effective means to expand their bumping capacity to meet the demand from display-driver IC manufacturers.” 

Mr. Sampus Yang, Vice President at Chipmore stated: “Chipmore offers a range of bumping solutions for our global customers, ranging from high-end gold bumping to cost-effective copper bumping for flip chip packaging. SPTS’s Sigma fxP PVD system produces high quality copper pillars with excellent throughput and low cost of ownership, which allows us to remain competitive in a highly cost-sensitive market. The additional bumping capability will allow us to capitalize on consumers’ growing appetite for higher resolution LCD displays and strengthen our reputation as a top packaging services company.”

Despite a slightly down first quarter, the semiconductor industry achieved near record growth in the second quarter of 2017, posting a 6.1 percent growth from the previous quarter, according to IHS Markit (Nasdaq: INFO). Global revenue came in at $101.4 billion, up from $95.6 billion in the first quarter of 2017. This is the highest growth the industry has seen in the second quarter since 2014.

The memory chip market set records in the second quarter, growing 10.7 percent to a new high of $30.2 billion with DRAM and NOR flash memory leading the charge, growing 14 percent and 12.3 percent quarter-on-quarter, respectively.

“The DRAM market had another quarter of record revenues on the strength of higher prices and growth in shipments,” said Mike Howard, director for DRAM memory and storage at IHS Markit. “Anxiety about product availability in the previous third and fourth quarters weighed on the industry. This led many DRAM buyers to build inventory — putting additional pressure on the already tight market. This year is shaping up to smash all DRAM revenue records and will easily pass the $60 billion mark.”

“For NOR, the supply-demand balance has tightened raising average selling prices and revenue,” said Clifford Leimbach, senior analyst for memory and storage at IHS Markit. “This mature memory technology has been in a steady decline for many years, but some market suppliers are reducing supply or leaving the market, which has tightened supply recently, resulting in the increase of revenue.”

In terms of application, consumer electronics and data processing saw the most growth, increasing in revenue by 7.9 percent and 6.8 percent, respectively, quarter-on-quarter. A lot of this growth can be attributed to the continual growth in memory pricing, as supply still remains tight.

Industrial semiconductors showed the third highest growth rate at 6.4 percent during the same period. This growth can be attributable to multiple segments, such as commercial and military avionics, digital signage, network video surveillance, HVAC, smart meters, traction, PV inverters, LED lighting and medical electronics including cardiac equipment, hearing aids and imaging systems.

Another trend in the industrial market is increasing factory automation, which alone is driving growth for discrete power transistors, thyristors, rectifiers and power diodes. The market for these devices is expected to reach $8 billion in 2021, up from $5.7 billion in 2015.

Intel remains the number one semiconductor supplier in the world, followed by Samsung Electronics by a slight margin. IHS Markit does not include foundry operations and other non-semiconductor revenue in the semiconductor market rankings.

Among the top 20 semiconductor suppliers, Advanced Micro Devices (AMD) and nVidia achieved the highest revenue growth quarter over quarter by 24.7 percent and 14.6 percent, respectively. There was no market share movement in the top 10 semiconductor suppliers. However, seven of the 10 companies in the 11 to 20 market share slots did change market share.

top_5_semiconductor_companies

JoshThe Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced Josh Shiode has joined the association as government affairs director. In this role, Shiode will help advance the U.S. semiconductor industry’s key legislative and regulatory priorities related to semiconductor research and technology, product security, and high-skilled immigration, among others. He also will serve as a senior representative of the industry before Congress, the White House, and federal agencies.

“The U.S. semiconductor industry is a key driver of America’s economic strength, national security, and global technology leadership,” said John Neuffer, SIA president and CEO. “Josh Shiode’s extensive knowledge, skills, and experience will make him an ideal advocate for our industry’s policy priorities in Washington, D.C. We’re thrilled to welcome him to the SIA team and look forward to his help advancing initiatives that promote growth and innovation in our industry and throughout the U.S. economy.”

Shiode most recently served as senior government relations officer at the American Association for the Advancement of Science (AAAS), where he helped guide the association’s science and technology advocacy before the executive and legislative branches. Previously, Shiode was a public policy fellow at the American Astronomical Society (AAS), where he helped develop and implement AAS’s government advocacy strategies. Shiode holds a doctorate in astrophysics from the University of California, Berkeley and a bachelor’s degree in astronomy and physics from Boston University.

Soitec, a designer and manufacturer of semiconductor materials for the electronics industry, is launching a pilot line to produce fully depleted silicon-on-insulator (FD-SOI) wafers in its Singapore wafer fab. This is the first stage in beginning FD-SOI production in Singapore and providing multi-site FD-SOI substrate sourcing to the global semiconductor market.

“Our decision to launch this FD-SOI line in Singapore as well as the decision we already made to ramp up our FD-SOI production in France are based on direct customer demand,” said Paul Boudre, CEO of Soitec. “These are very important milestones for Soitec and the expanding FD-SOI ecosystem. In Singapore, we plan to get full qualification at the customer level in the first half of 2019 and then increase capacity in line with market commitment.”

The FD-SOI ecosystem continues to strengthen and the use of FD-SOI technology is progressing. Multiple foundries, IDMs and fabless customers are engaged with a growing number of FD-SOI tape-outs and wafer starts. FD-SOI offers a unique value proposition for low-power applications, which makes it well suited for rapidly growing electronic market segments such as mobile processing, IoT, automotive and industrial.

Soitec reports that its investment in Singapore to launch its FD-SOI pilot line is approximately US$40 million, to be spent over a 24-month period.

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced new capabilities that complete its holistic, integrated design flow for TSMC’s advanced wafer-level Integrated Fan-Out (InFO) packaging technology. Additionally, Cadence has unveiled enhancements for TSMC’s chip-on-wafer-on-substrate (CoWoS) advanced packaging technology. The complete InFO flow and enhanced CoWoS design methodologies enable design teams to efficiently complete the development process, from planning to analysis across multiple dies.

Completed InFO Design Flow

The Cadence® tools that have been enhanced to complete the TSMC InFO flow include the Quantus™ QRC Extraction Solution, Physical Verification System (PVS), and the Voltus™ Sigrity™ Package Analysis solution. Additional tools in the flow include OrbitIO™ Interconnect Designer, System-in-Package (SiP) Layout, Sigrity XtractIM™ technology, Tempus™Timing Signoff Solution, Sigrity PowerDC™ technology and Sigrity PowerSI® 3D-EM Extraction Option. With the completion of the flow, system-on-chip (SoC) designers can now:

  • Create virtual interface blocks and automate parasitic extraction, enabling package-level cross-die timing analysis: Cadence provides the first available platform that offers cross-die coupling extraction via the Quantus QRC Extraction Solution and PVS, enabling InFO designers to efficiently complete timing analysis with the Tempus Timing Signoff Solution at the package level.
  • Perform power DC and root mean square (RMS) electromigration (EM) and signal EM analysis: The Voltus Sigrity Package Analysis solution provides an integrated platform for power analysis across multiple dies and InFO designs.

CoWoS Reference Flow Enhancements

Cadence has also developed enhancements to the TSMC CoWoS reference flow. The new capabilities within the CoWoS refence flow enable designers to perform:

  • Integrated electromagnetic interference (EMI) analysis that enables analysis of the CoWoS system: Cadence is now offering an updated Sigrity EMI flow with automatic design merging, enabling integrated EMI analysis, as well as broadband-frequency-dependent S-parameter simulation, allowing for E/H-field analysis of the CoWoS system.
  • Static/dynamic IR analysis from a single environment: Voltus IC Power Integrity Solution now allows designers to do static/dynamic IR analysis across die and silicon interposers concurrently, while also analyzing power EM (dynamic/static) and signal EM (peak/RMS/average) for both dies and interposers within a single tool environment.
  • Correct cross-die interface alignment among dies and interposers: The PVS design rule checking (DRC) and layout versus schematic (LVS) capabilities provide cross-die DRC and power/signal connectivity checks, ensuring the cross-die interface has the correct alignment among the dies and interposers.
  • Thermal analysis across the CoWoS package, allowing accurate thermal runway predictions and reduced EM pessimism: The Voltus IC Power Integrity Solution and Sigrity PowerDC technology enable designers to do layer-based thermal analysis across the CoWoS package, which includes automated power map generation for all die within the solution and layer-based temperature map generation.
  • Parasitic extraction for silicon interposers, enabling timing and electrical analysis: The Quantus QRC Extraction Solution offers performance RC extraction, generating Standard Parasitic Exchange Format (SPEF) data for cross-die timing analysis. Additionally, Cadence Sigrity XcitePI technology provides RCLK extraction for frequency domain, signal integrity and power integrity simulation.

“We see a strong demand from both mobile and high-performance computing customers wanting to quickly deploy systems based on TSMC’s advanced packaging technologies,” said Tom Beckley, senior vice president and general manager of the Custom IC & PCB Group at Cadence. “Through our close working relationship with TSMC, we have completed TSMC InFO design flow and enhanced TSMC CoWoS reference flow, enabling our mutual customers to further shorten design and verification cycle times so they can get to market faster.”

“The Cadence solution for InFO technology enables our customers to deliver designs with increased bandwidth within small form factors,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “With these enhancements, the integrated full-flow addresses the market need for faster design and verification cycles. Additionally, the new capabilities added to the Cadence solution for CoWoS supports our customers who want to utilize this holistic reference flow for advanced packaging projects.”

Entegris Inc. (NASDAQ: ENTG), a specialty materials provider, today announced the expansion of its Taiwan Technology Center for Research and Development (TTC) in Hsinchu, Taiwan.  The expansion adds a new Microcontamination Control Lab (MCL) that focuses on filtration media development and is home to the company’s relocated Asia Applications and Development Labs (AADL) for trace metal, organic contaminant, and nanoparticle analysis. This addition to the Center’s existing R&D, formulation scale-up, and pilot production capabilities also creates a single, off-site collaboration location for our customers’ specialty chemical, CMP and liquid filtration needs.

Key facts for the $8.5 million USD investment:

  • Class 1000 cleanroom
  • 5x increase in lab space
  • Facility renovations and equipment upgrades

“Interactions and dependencies between process materials and equipment are at a critical evolution point as device scaling continues to be a leading driver for efficient construction of today’s devices. Bringing the industry’s brightest minds together in a state-of-the-art facility enhances Entegris’ unique ability to meet these needs,” offered Entegris Chief Operations Officer, Todd Edlund. “By expanding the MCL facility, we bring together core-competencies in liquid filtration, specialty chemicals, and CMP to create more holistic analytical services and technology development solutions designed to meet our customer’s Logic, DRAM, and 3D NAND device manufacturing challenges.”

For more information on the new TTC and upgraded MCL lab, please visit the Entegris product display area, booth #176, during SEMICON Taiwan, Sept. 13-15, 2017, at the Taipei Nangang Exhibition Center.