Yearly Archives: 2017

Accelerometers and gyroscopes are fueling the robotic revolution, especially the drones’ market segment. However, these MEMS devices are not the only ones on the market place anymore, with environmental sensors penetrating this industry too.

InvenSense, today TDK, combined it: the US-based company, IMU leader and formerly Apple’s supplier during many years, released last month the world’s 1st 7-axis motion tracking device combining accelerometer, gyroscope and pressure sensor. InvenSense announces the ICM-20789 7-axis combo sensor dedicated to mainly drones and flying toys as well as smart watches, wearables, activity monitoring, floor and stair counting etc.

The reverse costing company, System Plus Company has investigated the 7-axis component and technologies selected by InvenSense. Aim of this analysis was to identify the technologies selected by the leading company as well as to understand the impacts on the manufacturing costs.

What are the technical choices made by InvenSense? What are the benefits for the device in term of performances? What is the impact on the manufacturing process flow?

System Plus Consulting’s team proposes today a comprehensive technology and cost analysis, including as well a detailed comparison with the previous generation of combo sensors from InvenSense.

ILLUS_INVENSENSE_TDK_ReverseEngineering_SYSTEMPLUSCONSULTING_Dec2017

The drone’s market segment dedicated to consumer applications confirms its attractiveness with 23% CAGR between 2016 and 2021. According to Yole Développement, sister company of System Plus Consulting, the market should reach almost US$ 3.4 billion in 2023 (Source : Sensors for drones and robots: market opportunities and technology revolution report, Yole Développement, 2016). Under this dynamic context, System Plus Consulting’s experts are following the technical advances and the evolution of the manufacturing costs of the combo devices. InvenSense’s device is a good example of this technology breakthrough: indeed, for the 1st time, a company presents a 7-axis component combining accelerometer, gyroscope and barometric pressure sensor, integrated on the same package. Innovation clearly is not in the selection of the components, comments the reverse engineering & costing company, but more in the smart combination of the three devices in the same package.

Stéphane Elisabeth, RF and Advanced Packaging Cost Engineer from System Plus Consulting explains“Using single package integration, the US company merged a 6-axis inertial sensor already identified in iPhone 6 with a barometric pressure sensor based on a design coming from the barometric division of Sensirion. Therefore, InvenSense took benefits of Sensirion’s partial acquisition, taking place in 2016, by developing a specific approach eliminating a package and minimizing board area requirements.”

ILLUS_INVENSENSE_TDK_Combo_CostBreakdown_SYSTEMPLUSCONSULTING_Dec2017

InvenSense was able to integrate its own barometric pressure sensor thanks to the knowledge reached with the acquisition of Sensirion’s barometric division. This device is shipped in a 4 mm x 4 mm x 1.37 mm land grid array (LGA) package.

InvenSense acquired the pressure sensor business from Sensirion Holding AG and its affiliates used in the development of capacitive-type monolithic digital pressure-sensor technology platform.

InvenSense’s financial report highlights the details of this acquisition: the purchase price associated with the acquisition was approximately US$9.8 million, of which US$5.7 million was allocated to developed technology with an estimated useful life of six years and US$4.1 million was allocated to goodwill.

Faced with this simple but impressive technical innovation, what will be the answer of other MEMS & Sensors manufacturers? Will this combination of IMU with barometric pressure sensor be followed by competitors? The selling prices of IMUs have fell in recent years and adding new functions is a way to keep a profitable ASP.

Researchers at Aalto University, Finland, have developed a biosensor that enables creating a range of new easy-to-use health tests similar to home pregnancy tests. The plasmonic biosensor can detect diseased exosomes even by the naked eye. Exosomes, important indicators of health conditions, are cell-derived vesicles that are present in blood and urine.

A rapid analysis by biosensors helps recognize inflammatory bowel diseases, cancer and other diseases rapidly and start relevant treatments in time. In addition to using discovery in biomedicine, industry may use advanced applications in energy.

Researchers created a new biosensor by depositing plasmonic metaparticles on a black, physical body that absorbs all incident electromagnetic radiation. A plasmon is a quantum of plasma oscillation. Plasmonic materials have been used for making objects invisible in scientific tests. They efficiently reflect and absorb light. Plasmonic materials are based on the effective polarizabilities of metallic nanostructures.

The carriers containing Ag nanoparticles are covered with various dielectrics of AlN, SiO2 and the composites thereof that are placed on a black background to enhance the reflectivity contrast of various colours at a normal angle of incidence. Credit: Aalto University

The carriers containing Ag nanoparticles are covered with various dielectrics of AlN, SiO2 and the composites thereof that are placed on a black background to enhance the reflectivity contrast of various colours at a normal angle of incidence. Credit: Aalto University

“It is extraordinary that we can detect diseased exosomes by the naked eye. The conventional plasmonic biosensors are able to detect analytes solely at a molecular level. So far, the naked-eye detection of biosamples has been either rarely considered or unsuccessful”, says Professor Mady Elbahri from Aalto University.

Plasmonic dipoles are famous for their strong scattering and absorption. Dr. Shahin Homaeigohar and Moheb Abdealziz from Aalto University explain that the research group has succeeded in demonstrating the as-yet unknown specular reflection and the Brewster effect of ultrafine plasmonic dipoles on a black body host.

“We exploited it as the basis of new design rules to differentiate diseased human serum exosomes from healthy ones in a simple manner with no need to any specialized equipment”, says Dr. Abdou Elsharawy from the University of Kiel.

The novel approach enables a simple and cost-effective design of a perfect colored absorber and creation of vivid interference plasmonic colors.

According to Elbahri, there is no need to use of sophisticated fabrication and patterning methods. It enables naked-eye environmental and bulk biodetection of samples with a very minor change of molecular polarizability of even 0.001%.

Think keeping your coffee warm is important? Try satellites. If a satellite’s temperature is not maintained within its optimal range, its performance can suffer which could mean it could be harder to track wildfires or other natural disasters, your Google maps might not work and your Netflix binge might be interrupted. This might be prevented with a new material recently developed by USC Viterbi School of Engineering engineers.

When satellites travel behind the Earth, the Earth can block the sun’s rays from reaching the satellites—cooling them down. In space, a satellite can face extreme temperature variation as much as 190 to 260 degrees Fahrenheit. It’s long been a challenge for engineers to keep satellite temperatures from fluctuating wildly. Satellites have conventionally used one of two mechanisms: physical “shutters” or heat pipes to regulate heat. Both solutions can deplete on-board power reserves. Even with solar power, the output is limited. Furthermore, both solutions add mass, weight and design complexity to satellites, which are already quite expensive to launch.

Taking cues from humans who have a self-contained system to manage internal temperature through homeostasis, a team of researchers including Michelle L. Povinelli, a Professor in the Ming Hsieh Department of Electrical Engineering at the USC Viterbi School of Engineering, and USC Viterbi students Shao-Hua Wu and Mingkun Chen, along with Michael T. Barako, Vladan Jankovic, Philip W.C. Hon and Luke A. Sweatlock of Northrop Grumman, developed a new material to self-regulate the temperature of the satellite. The team of engineers with expertise in optics, photonics, and thermal engineering developed a hybrid structure of silicon and vanadium dioxide with a conical design to better control the radiation from the body of the satellite. It’s like a textured skin or coating.

Vanadium dioxide functions as what is known as a “phase-change” material. It acts in two distinct ways: as an insulator at low temperatures and a conductor at high temperatures. This affects how it radiates heat. At over 134 degrees Fahrenheit (330 degrees Kelvin), it radiates as much heat as possible to cool the satellite down. At about two degrees below this, the material shuts off the heat radiation to warm the satellite up. The material’s conical structure (almost like a prickly skin) is invisible to the human eye at about less than half the thickness of a single human hair–but has a distinct purpose of helping the satellite to switch its radiation on and off very effectively.

Results

The hybrid material developed by USC and Northrop Grumman is twenty times better at maintaining temperature than silicon alone. Importantly, passively regulating heat and temperature of satellites could increase the life span of the satellites by reducing the need to expend on-board power.

Applications on Earth

Besides use on a satellite, the material could also be used on Earth for thermal management. It could be applied to a building over a large area to more efficiently maintain a building’s temperature.

The study, “Thermal homeostasis using microstructured phase-change materials,” is published in Optica. The research was funded by Northrop Grumman and the National Science Foundation. This development is part of a thematic research effort between Northrop Grumman, NG Next Basic Research and USC known as the Northrop Grumman Institute of Optical Nanomaterials and Nanophotonics (NG-ION2).

The researchers are now working on developing the material in the USC microfabrication facility and will likely benefit from the new capabilities in the recently-dedicated John D. O’Brien Nanofabrication Laboratory in the USC Michelson Center for Convergent Bioscience.

Industry enters the age of WOW


December 13, 2017

By Christian G. Dieseldorff, Industry Research & Statistics Group, SEMI, Milpitas, California

The semiconductor industry has been there before, with large increases in investments followed by dramatic downturns. While the most dramatic downturns, 2001 and 2009, were due to, in a large part, acro-economic factors, the industry has typically observed one to two years of increased investment spending followed by a down period. This time around, the industry will achieve a “WOW” with three consecutive years of fab investment growth, a pattern not observed since the mid-1990s.

Why are things different this time?  A diverse array of technology drivers promise more robust long-term growth, such as Mobile applications, Internet of Things (IoT), Automotive & Robotics, Industrial, Augmented Reality & Virtual Reality (AR&VR), Artificial Intelligence (AI), and 5G networking. Each of these new technologies inspires a big “WOW” as the industry embarks on the beginning of a promising journey of growth.

Driven by these technologies, on average the semiconductor revenue CAGR from 2016 to 2021 is forecasted to be 6 percent (in comparison to the previous 2011-2016 CAGR of 2.3 percent). For the first time in the industry’s history, semiconductor revenues will exceed the US$400 billion revenue milestone in 2017. Demand for chips is high, pricing is strong for memory, and the competition is fierce. All of this is spurring increased fab investments, with many companies investing at previously unseen levels for new fab construction and fab equipment. See Figure 1.

Figure 1

Figure 1

The World Fab Forecast report, published on December 4, 2017, by SEMI, is modeling that fab equipment spending in 2017 will total US$57 billion or 41 percent year-over-year (YoY) growth. In 2018, spending is expected to shoot up another 11 percent at US$63 billion. The two spending jumps in 2017 and 2018 are contributing to the “WOW” factor and to two consecutive years of record fab investments. Following historic large investments, some slowdown is expected for 2019.

Many companies, such as Intel, Micron, Toshiba (and Western Digital), and GLOBALFOUNDRIES, have increased fab investments in 2017 and 2018; however, the strong increases we see in both years are not caused by these companies but by one company and primarily one region. See Figure 2.

Figure 2

Figure 2

The first jump – a Big WOW – in 2017 is the surge of investments in Korea, due mainly to Samsung. Samsung is expected to increase its fab equipment spending by 128 percent in 2017 from US$8 billion to US$18 billion. No single company has invested so much in a single year in its fabs and much of its spending is in Korea. SK Hynix also increased fab equipment spending, by about 70 percent, to US$5.5 billion, its largest spending level in its history.  While the bulk of Samsung’s and SK Hynix’s spending remains in Korea, some will also go to China, and in the case of Samsung to the United States. Both Samsung and SK Hynix are expected to maintain high levels of investments for 2018.

The second jump – another WOW – is investment growth for 2018 in China. China is expected to begin equipping the many fabs that were constructed in 2017. In the past, non-Chinese companies made the majority of the fab investments in China but for the first time in 2018, Chinese-owned companies will approach parity, spending nearly as much on fab equipment as non-Chinese device manufacturers.

Between 2013 and 2017, fab equipment spending in China by Chinese-owned companies typically ranged between US$1.5 billion to US$2.5 Billion per year, while non-Chinese companies invested between US$2.5 billion to US$5 billion per year. In 2018, Chinese-owned companies are expected to invest about US$5.8 billion, while non-Chinese will invest US$6.7 billion. Many new companies such as Yangtze Memory Technology, Fujian Jin Hua, Hua Li, and Hefei Chang Xin Memory are investing heavily in the region.

New fabs being built

Historic highs in equipment spending in 2017 and 2018 reflect growing demand. This spending follows unprecedented growth in construction spending for new fabs also detailed in SEMI’s World Fab Forecast report. Construction spending will reach all-time highs with China construction spending taking the lead: US$6 billion in 2017 and US$6.6 billion in 2018, shattering another record – no region has ever spent more than US$6 billion in a single year for construction. More new fabs mean another wave of spending on equipping fabs in the next few years. See Figure 3.

Fab-forecast-Chart3

Figure 3

Considering all of these “WOW” factors, there is good reason to feel positive about the semiconductor industry. Even with a slowdown, the industry has and will continue to enjoy a positive outlook for long-term growth. In the meantime, hold on tight and enjoy the “WOW.”

More details are available in SEMI’s just-published World Fab Forecast, December 4, 2017, edition which covers quarterly data (spending, capacity, technology nodes, wafer sizes, and product types) per fab until end of 2018.

Throughout 2017, DRAM manufacturers faced pressure to boost output of their devices—particularly high-performance DRAM used in data center servers, and low-power high-density DRAM used in smartphones and other mobile products. Strong, ongoing demand put significant upward pressure on DRAM average selling prices.  This trend continued into 4Q17 and is expected to drive quarterly DRAM sales to an all time high mark of $21.1 billion (Figure 1), capping an incredible year of growth in which DRAM sales set a new all time high sales mark each quarter. The forecast $21.1 billion sales level in 4Q17 would be an increase of 65% compared to the $12.8 billion DRAM market of 4Q16.

Figure 1

Figure 1

Annual DRAM market growth of 74% is forecast for 2017, which would be the highest growth rate since the 78% increase in 1994—23 years ago—and 61 points more than the 13% average DRAM market growth rate from 1993-2017 (Figure 2).  The expected 74% DRAM market growth in 2017 will mark the fourth time since 1993 that the DRAM market has increased by more than 50%.  This near-historic high market spike in 2017 was brought on by several factors, including constrained supply attributed to a lack of major fab expansion plans, yield difficulties with leading-edge (≤20nm) processes, demand for high performance (graphics) DRAM from gaming systems and data center-based server applications, and increased average content for mobile DRAM used in smartphones.

Figure 2

Figure 2

There is an increasing need for high-speed but inexpensive data storage in smartphone handsets for multi-tasking, which is boosting the average DRAM content in a smartphone.  The Apple iPhone 8 features 2GB of DRAM and the iPhone X has 3GB of DRAM.  The Samsung Galaxy S8 is sold with 4GB of DRAM (6GB in China).  Huawei’s P10 Plus, and HTC’s U11 come with 6GB of DRAM.  The One Plus 5 model and the first smartphone from Razer, a Singapore-based company that is primarily known for its video game equipment, have 8GB of DRAM.

With virtual and augmented reality and artificial intelligence becoming prominent features on new smartphones and apps, DRAM content in high-end smartphones shows no signs of slowing.  Meanwhile, DRAM growth for smartphones is also stemming from less developed countries, where much of the population is moving from feature phones to their first smartphone—literally transitioning from zero to 1GB of mobile DRAM.

Based on historical trends, the DRAM industry will likely experience a decline (possibly a big market decline) in its growth rate in the not-too-distant future as prices begin to tumble with significant capacity additions and an increase in DRAM output expected over the next year or two.  Announcements by Samsung and SK Hynix in the second half of 2017 confirmed that new DRAM capacity is set to come online in 2018, which likely will ease the upward trend of DRAM ASPs next year.  Samsung has stated its semiconductor capital expenditure budget for 2017 will be an enormous $26.0 billion, and SK Hynix has announced plans to build a new manufacturing line at its massive facility in Wuxi, China.  Micron has gone on record as saying it doubts that it will ever need to build another new DRAM fab, but it is hard to imagine that Micron will sit still as its two fiercest rivals capture additional marketshare.  (For the record, Micron and Intel are developing Crosspoint memory as a potential replacement for DRAM).

aveni S.A., developer and manufacturer of market-disrupting wet deposition technologies and chemistries for 2D interconnects and 3D through silicon via packaging, today announced it has obtained results that strongly support the continued use of copper in the back end of line (BEOL) for advanced interconnects, at and beyond the 5nm technology node.

“In this 20th-anniversary year of copper integration, our results validate the comments made by IBM Research Fellow Dan Edelstein in his keynote presentation at the recent IEEE Nanotechnology Symposium, discussing that copper integration is here to stay,” noted Bruno Morel, aveni CEO.

As devices inevitably continue to shrink to meet (and create) market demand, designers are exploring alternative integration schemes, not only for the front end of line, but also the BEOL. This includes, most notably, replacing the copper in dual-damascene interconnects, to compensate for the increased resistance-capacitance (RC) delay that accompanies the thinner copper wires and adversely affects device speed. Proposed replacement options for copper are cobalt, the most likely candidate, or more exotic materials like ruthenium, graphene or carbon nanotubes.

Advanced dual-damascene structures employ an atomic layer deposition tantalum nitride (TaN) copper diffusion barrier, a thin chemical vapor deposition (CVD) cobalt liner, and the electroplated copper fill layer, which makes up most of the wiring. Earlier generations (≥7nm node) also use a physical vapor deposition (PVD) copper seed layer between the cobalt and copper fill, but advanced devices are phasing out this film due to marginal seed coverage and integration hurdles.

Of particular interest is the thin TaN barrier, which prevents copper from diffusing into and poisoning the device. The integrity of the thin cobalt liner (on top of TaN) is critical to ensuring that the barrier functions properly. The reduced thickness of cobalt liners for the 5nm technology node is approaching 3nm, reducing process flexibility for conventional approaches to copper plating.

In a recent study, aveni compared its Sao™ alkaline-based copper electroplating chemistry performance with a conventional, commercially available acidic copper plating chemistry. The samples to be plated were 3nm CVD cobalt over TaN. The study results showed that the acidic copper chemistry attacked the cobalt liner, causing the plating chemistry to react with the underlying TaN film and form tantalum oxide (TaOx). TaOx formation is another failure mode of devices, because it creates an effective open circuit that prevents current flow.

With aveni’s Sao chemistry, the cobalt remained intact and TaOx was not formed, which enables the extension of copper interconnects to process nodes at 5nm and below.

Frédéric Raynal, chief technical officer at aveni, commented, “We were extremely excited about these results, because they substantiate our position that Sao alkaline-based chemistry for copper electroplating is superior to acidic chemistries, especially with the thinner cobalt liners used in advanced nodes.”

aveni will publish the complete findings in a report in early 2018.

 

In a major step toward making a quantum computer using everyday materials, a team led by researchers at Princeton University has constructed a key piece of silicon hardware capable of controlling quantum behavior between two electrons with extremely high precision. The study was published Dec. 7 in the journal Science.

The researchers demonstrated the ability to control with precision the behavior of two silicon-based quantum bits, or qubits, paving the way for making complex, multi-qubit devices using technology that is less expensive and easier to manufacture than other approaches. Credit: David Zajac, Princeton University

The researchers demonstrated the ability to control with precision the behavior of two silicon-based quantum bits, or qubits, paving the way for making complex, multi-qubit devices using technology that is less expensive and easier to manufacture than other approaches. Credit: David Zajac, Princeton University

The team constructed a gate that controls interactions between the electrons in a way that allows them to act as the quantum bits of information, or qubits, necessary for quantum computing. The demonstration of this nearly error-free, two-qubit gate is an important early step in building a more complex quantum computing device from silicon, the same material used in conventional computers and smartphones.

“We knew we needed to get this experiment to work if silicon-based technology was going to have a future in terms of scaling up and building a quantum computer,” said Jason Petta, a professor of physics at Princeton University. “The creation of this high-fidelity two-qubit gate opens the door to larger scale experiments.”

Silicon-based devices are likely to be less expensive and easier to manufacture than other technologies for achieving a quantum computer. Although other research groups and companies have announced quantum devices containing 50 or more qubits, those systems require exotic materials such as superconductors or charged atoms held in place by lasers.

Quantum computers can solve problems that are inaccessible with conventional computers. The devices may be able to factor extremely large numbers or find the optimal solutions for complex problems. They could also help researchers understand the physical properties of extremely small particles such as atoms and molecules, leading to advances in areas such as materials science and drug discovery.

Building a quantum computer requires researchers to create qubits and couple them to each other with high fidelity. Silicon-based quantum devices use a quantum property of electrons called “spin” to encode information. The spin can point either up or down in a manner analogous to the north and south poles of a magnet. In contrast, conventional computers work by manipulating the electron’s negative charge.

Achieving a high-performance, spin-based quantum device has been hampered by the fragility of spin states — they readily flip from up to down or vice versa unless they can be isolated in a very pure environment. By building the silicon quantum devices in Princeton’s Quantum Device Nanofabrication Laboratory, the researchers were able to keep the spins coherent — that is, in their quantum states — for relatively long periods of time.

To construct the two-qubit gate, the researchers layered tiny aluminum wires onto a highly ordered silicon crystal. The wires deliver voltages that trap two single electrons, separated by an energy barrier, in a well-like structure called a double quantum dot.

By temporarily lowering the energy barrier, the researchers allow the electrons to share quantum information, creating a special quantum state called entanglement. These trapped and entangled electrons are now ready for use as qubits, which are like conventional computer bits but with superpowers: while a conventional bit can represent a zero or a 1, each qubit can be simultaneously a zero and a 1, greatly expanding the number of possible permutations that can be compared instantaneously.

“The challenge is that it’s very difficult to build artificial structures small enough to trap and control single electrons without destroying their long storage times,” said David Zajac, a graduate student in physics at Princeton and first-author on the study. “This is the first demonstration of entanglement between two electron spins in silicon, a material known for providing one of the cleanest environments for electron spin states.”

The researchers demonstrated that they can use the first qubit to control the second qubit, signifying that the structure functioned as a controlled NOT (CNOT) gate, which is the quantum version of a commonly used computer circuit component. The researchers control the behavior of the first qubit by applying a magnetic field. The gate produces a result based on the state of the first qubit: If the first spin is pointed up, then the second qubit’s spin will flip, but if the first spin is down, the second one will not flip.

“The gate is basically saying it is only going to do something to one particle if the other particle is in a certain configuration,” Petta said. “What happens to one particle depends on the other particle.”

The researchers showed that they can maintain the electron spins in their quantum states with a fidelity exceeding 99 percent and that the gate works reliably to flip the spin of the second qubit about 75 percent of the time. The technology has the potential to scale to more qubits with even lower error rates, according to the researchers.

“This work stands out in a worldwide race to demonstrate the CNOT gate, a fundamental building block for quantum computation, in silicon-based qubits,” said HongWen Jiang, a professor of physics and astronomy at the University of California-Los Angeles. “The error rate for the two-qubit operation is unambiguously benchmarked. It is particularly impressive that this extraordinarily difficult experiment, which requires a sophisticated device fabrication and an exquisite control of quantum states, is done in a university lab consisting of only a few researchers.”

ProPlus Design Solutions Inc. and MPI Corporation today announced a strategic partnership agreement and immediate availability of a characterization and modeling solution that integrates ProPlus’ SPICE modeling and noise characterization solution with MPI’s advanced probing technologies.

The integrated solution offers seamless support of the MPI probe stations to perform automated measurement of DC, CV and noise characteristics, enabling MPI users easy access to the most accurate ProPlus SPICE modeling and noise characterization offerings. The advanced probing technologies developed by MPI are optimized for the latest ProPlus 9812DX noise analyzer with improved grounding and shielding technologies critical to wafer-level noise characterization.

Under the partnership agreement, ProPlus users are able to integrate MPI’s advanced semi-automatic probe stations in their characterization and modeling flow for better noise measurement quality. The close collaboration also proved that probe card wafer-level noise characterization is possible using the 9812DX noise analyzer. Previously, these measurements were performed using manipulators and easily introducing RF interferences and oscillations. The advanced probe card technology specially developed for noise measurement provides better data quality and stability, as well as improves flexibility of wafer-level noise characterization for higher throughput.

“ProPlus Design Solutions continues to invest on improving the technologies that made wafer-level noise characterization possible 20 years ago,” remarks Dr. Zhihong Liu, chairman and chief executive officer of ProPlus Design Solutions. “We brought it to the next level with a specially designed probe card for a tightly integrated noise system thus delivering the fastest and most accurate noise characterization of the highest quality. We’re pleased to work with MPI on this effort.”

“The collaboration with ProPlus Design Solutions has enabled a seamlessly integrated wafer level low-frequency noise measurement capability with guaranteed system configuration and performance,” says Dr. Stojan Kanev, general manager of Advanced Semiconductor Test Division at MPI Corporation. “We now offer the most advanced high throughput noise characterization and modeling system. MPI’s exceptional shielding technology provides world class 1/f noise measurement capability. Customers may now rest assured these systems are validated to provide reliable and accurate noise measurement capability while enjoying a reduced cost of test.”

The integrated solution has been adopted by leading semiconductor companies. ProPlus and MPI Corporation will demonstrate the joint solution globally throughout 2018.

SUNY Polytechnic Institute (SUNY Poly) Professor of Nanoengineering Bin Yu has been named a Fellow of the National Academy of Inventors (NAI), the organization announced Tuesday. Election to NAI Fellow status is one of the highest professional accolades bestowed solely to academic inventors who have demonstrated a prolific spirit of innovation in creating or facilitating outstanding inventions that have made a tangible impact on quality of life, economic development, and the welfare of society.

“I am proud to congratulate Dr. Yu on his selection as Fellow of the NAI, which is a strong reflection of his research that has helped to advance cutting-edge nanotechnologies,” said SUNY Poly Interim President Dr. Bahgat Sammakia. “Dr. Yu’s numerous patents and continued SUNY Poly-based research in exciting areas such as nanomaterials and advanced nano-devices continues to hold promise for further developments that can enhance energy efficiency and boost computing speeds to improve the technologies that our society relies on each day.”

Those elected to the rank of NAI Fellow are named inventors on U.S. patents and were nominated by their peers for outstanding contributions to innovation, as well as for patents and licensing, innovative discovery and technology, and providing significant impact on society.

Dr. Yu has a number of significant accomplishments in the areas of nano electronic devices, nano-based sensors, nano-based energy harvesting, emerging data storage devices, next-generation interconnects, and smart nano-manufacturing, including work as the lead researcher for the world’s first 10 nm gate-length 3D transistor FinFET (IEEE-IEDM’2002), and for the world’s first THz silicon logic switch (IEEE-IEDM’2001).

Dr. Yu is the recipient of multiple awards and honors, including the NASA Innovation Award and IBM Faculty Award, and was ranked #3 by the National Science Foundation for Supported Investigators with Most Patents in 2011; as an inventor, he holds more than 300 awarded U.S. patents.

“I am honored that I have been selected to become a National Academy of Inventors Fellow, a powerful recognition of the work undertaken at SUNY Poly which can help to advance technology based on a wide variety of applied nanostrucutures,” said Dr. Yu. “I congratulate my fellow inductees and appreciate the acknowledgement of the importance of these research contributions that have led to more than 300 U.S. patents. I look forward to continuing to pursue efforts utilizing SUNY Poly’s state-of-the-art resources and capabilities for research related to nano-inspired technologies targeted for the next-generation of computing, sensing, and energy generation, as well as research related to emerging nanomaterials for smart nanomanufacturing.”

Dr. Yu has published books and book chapters on topics ranging from graphene-based electronics to 2D layered semiconductor-based emerging solar photovoltaics. He has also served as Editor of IEEE Electron Device Letters from 2001-2007, Associate Editor of IEEE Transactions on Nanotechnology from 2007-2010, and is currently an Editorial Board Member for Nano-Micro Letters and an Editorial Advisory Board Member for Nanoelectronics and Spintronics, among other leadership positions. Dr. Yu has been invited as a speaker to more than 100 highlight/invited talks, seminars, and tutorials to international conferences, universities, industry national labs, and professional societies. He is also an Institute of Electrical and Electronics Engineers (IEEE) Fellow and IEEE Electronic Device Society Distinguished Lecturer. More information about Dr. Yu’s background can be found here.

With the election of the 2017 class there are now 912 NAI Fellows, representing over 250 research universities and governmental and non-profit research institutes. The 2017 Fellows are named inventors on nearly 6,000 issued U.S. patents, bringing the collective patents held by all NAI Fellows to more than 32,000 issued U.S. patents.

Included among all NAI Fellows are more than 100 presidents and senior leaders of research universities and non-profit research institutes; 439 members of the National Academies of Sciences, Engineering, and Medicine; 36 inductees of the National Inventors Hall of Fame; 52 recipients of the U.S. National Medal of Technology and Innovation and U.S. National Medal of Science; 29 Nobel Laureates; 261 AAAS Fellows; 168 IEEE Fellows; and 142 Fellows of the American Academy of Arts & Sciences, among other awards and distinctions.

In April 2018 the 2017 NAI Fellows will be inducted as part of the Seventh Annual NAI Conference of the National Academy of Inventors at the Mayflower Hotel, Autograph Collection in Washington, D.C., and Andrew H. Hirshfeld, U.S. Commissioner for Patents, will provide the keynote address for the induction ceremony.

The 2017 class of NAI Fellows was evaluated by the 2017 Selection Committee, which included 18 members comprising NAI Fellows, U.S. National Medals recipients, National Inventors Hall of Fame inductees, members of the National Academies of Sciences, Engineering, and Medicine and senior officials from the USPTO, National Institute of Standards and Technology, Association of American Universities, American Association for the Advancement of Science, Association of Public and Land-grant Universities, Association of University Technology Managers, and National Inventors Hall of Fame, among other organizations.

Today, SEMI, the global industry association representing the electronics manufacturing supply chain, released its Year-end Forecast at the annual SEMICON Japan exposition. SEMI projects that worldwide sales of new semiconductor manufacturing equipment will increase 35.6 percent to US$55.9 billion in 2017, marking the first time that the semiconductor equipment market has exceeded the previous market high of US$47.7 billion set in 2000. In 2018, 7.5 percent growth is expected to result in sales of US$60.1 billion for the global semiconductor equipment market – another record-breaking year.

The SEMI Year-end Forecast predicts a 37.5 percent increase in 2017, to $45.0 billion, for wafer processing equipment. The other front-end segment, which consists of fab facilities equipment, wafer manufacturing, and mask/reticle equipment, is expected to increase 45.8 percent to $2.6 billion. The assembly and packaging equipment segment is projected to grow by 25.8 percent to $3.8 billion in 2017, while semiconductor test equipment is forecast to increase by 22.0 percent to $4.5 billion this year.

In 2017, South Korea will be the largest equipment market for the first time. After maintaining the top spot for five years, Taiwan will place second, while China will come in third. All regions tracked will experience growth, with the exception of Rest of World (primarily Southeast Asia). South Korea will lead in growth with 132.6 percent, followed by Europe at 57.2 percent, and Japan at 29.9 percent.

SEMI forecasts that in 2018, equipment sales in China will climb the most, 49.3 percent, to $11.3 billion, following 17.5 percent growth in 2017. In 2018, South Korea, China, and Taiwan are forecast to remain the top three markets, with South Korea maintaining the top spot at $16.9 billion. China is forecast to become the second largest market at $11.3 billion, while equipment sales to Taiwan are expected to approach $11.3 billion.

The following results are in terms of market size in billions of U.S. dollars:

equipment forecast