Yearly Archives: 2017

IBM’s Khare on A.I.

December 7, 2017

BY PETE SINGER, Editor-in-Chief

Mukesh Khare, VP of IBM Research, talked about the impact artificial intelligence (AI) is going to have on the semiconductor industry during a recent panel session hosted by Applied Materials. He said that today most artificial intelligence is too complex. It requires, training, building models and then doing inferencing using those models. “The reason there is good in artificial intelligence is because of the exponential increase in data, and cheap compute. But, keep in mind that, the compute that we are using right now is the old compute. That compute was built to do spreadsheet, databases, the traditional compute.

“Since that compute is cheap and available, we are making use of it. Even with the cheap and available compute in cloud, it takes months to generate those models. So right now, most of the training is still being done in cloud. Whereas, inferencing, making use from that model is done at the edge. However, going forward, it is not possible because the devices at the edge are continuously generating so much data that you cannot send all the data back to the cloud, generate models, and come back on the edge.

“Eventually, a lot of training needs to move to the edge as well,” Khare said. This will require some innovation so that the compute, which is being done right now in cloud, can be transferred over to edge with low-power devices, cheap devices. Applied Materials’ CIO Jay Kerley added that innovation has to happen not only at the edge, but in the data center and at the network layer, as well as in the software frameworks. “Not only the AI frameworks, but what’s driving compression, de-duplication at the storage layer is absolutely critical as well,” he said.

Khare also weighed in on how transistors and memory will need to evolve to meet the demands of new AI computer architec- tures, “For artificial intelligence in our world, we have to think very differently. This is an inflection, but this is the kind of inflection that world has not seen for last 60 years.” He said the world has gone from tabulating system era (1900 to 1940) to the programmable system era in 1950s, which we are still using. “We are entering the era of what we call cognitive computing, which we believe started in 2011, when IBM first demonstrated artificial intelligence through our Watson System, which played Jeopardy,” he said.

Khare said “we are still using the technology of programmable systems, such as logic, memory, the traditional way of thinking, and applying it to AI, because that’s the best we’ve got.”
AI needs more innovation at all levels, Khare said. “You have to think about systems level optimization, chip design level optimization, device level optimization, and eventually materials level optimization,” he said. “The artificial workloads that are coming out are very different. They do not require the traditional way of thinking — they require the way the brain thinks. These are the brain inspired systems that will start to evolve.”

Khare believes analog compute might hold the answer. “Analog compute is where compute started many, many years ago. It was never adopted because the precision was not high enough, so there were a lot of errors. But the brain doesn’t think in 32 bits, our brain thinks analog, right? So we have to bring those technologies to the forefront,” he said. “In research at IBM we can see that there could be several orders of magnitude reduction in power, or improvement in efficiency that’s possible by intro- ducing some of those concepts, which are more brain inspired.”

Christos Georgiopoulos (former Intel VP and professor who was also on the panel) said a new compute model is required for A.I. “It’s important to understand that the traditional workloads that we all knew and loved for the last forty years, don’t apply with A.I. They are completely new workloads that require very different type of capabilities from the machines that you build,” he said. “With these new kind of workloads, you’re going to require not only new architectures, you’re going to require new system level design. And you’re going to require new capabilities like frameworks. He said TensorFlow, which is an open-source software library for machine intelligence originally developed by researchers and engineers working on the Google Brain Team, seems to be the biggest framework right now. “Google made it public for only one very good reason. The TPU that they have created runs TensorFlow better than any other hardware around. Well, guess what? If you write something on TensorFlow, you want to go to the Google backend to run it, because you know you’re going to get great results. These kind of architectures are getting created right now that we’re going to see a lot more of,” he said.

3D acoustic images expand their usefulness

December 7, 2017

BY TOM ADAMS, Sonoscan, Inc., Elk Grove Village, IL

Three-dimensional acoustic images, like three-dimensional light images, differ from their two-dimensional counterparts by displaying the z dimension in addition to x and y dimensions. The first 3D acoustic images were made around by 20 years ago at Sonoscan, who invented the technique. The technology can display the surface topography of a sample, or its internal profile at a desired depth.

The C-SAM® acoustic micro imaging tools that make the 3D images have a transducer that pulses ultrasound at a given frequency at or into the sample thousands of times a second as the transducer scans back and forth above the surface of the sample. A pulse of ultrasound leaving the transducer travels first through a water couplant, supplied constantly by a water jet attached to the transducer. Every time ultrasound exits one material/fluid and enters another, some of the ultra- sound is reflected to the transducer; as a result, a portion of the pulse is reflected by the water-to-sample surface interface. The rest of the pulse crosses the surface interface and travels deeper into the sample.

In most acoustic imaging, the concern is with the amplitude of the returned echoes from the interior of the sample. A well bonded interface between silicon and epoxy will reflect a small amount of the pulse. The amount of ultrasound reflected causes a specific amplitude in the return echo. The echo amplitude is measured and then displayed in the acoustic image by an assigned color value for that amplitude. The highest amplitude echoes essentially indicate 100% reflection and are produced only by the interface between a solid and a gas. All gap-type defects meet this definition.

By measuring the amplitude of the reflected signal and identifying those having near-total reflection, an acoustic micro imaging (AMI) tool can detect voids, cracks, non-bonds and other gap-type anomalies that threaten the longevity of a part.

3D imaging, however, cares about the position in time of a reflection from a given plane such as the surface of the sample. By measuring the distance, in time, from the end of the transducer to the front surface, AMI can assign a color value to each location in time that the front surface occurs. In this way a color represen- tation of the topography is made. Plastic BGA packages, for example, are notorious for having internal defects that disturb the flatness of the package’s surface. By assigning a color to each height variation, the locations of surface disturbances are easily detected. The same method can be used to image unpopulated printed circuit boards to ensure that they are flat enough to avoid placing stress on connections. Samples imaged in 3D are viewed at an angle from the vertical perspective in order to make local height differences visible.

Recently the method has been used in a different role – measuring the height, before substrate attachment, of the solder bumps on BGAs. A precise vertical range is set – in acoustic terms, a gate. If the tops of all the solder bumps fall within the small vertical range defined by the gate, successful bonding of all bumps to the substrate is more likely.

The basics of imaging rounded bumps are essentially the same as for imaging flat surfaces. The sides of the bump may send back little or no signal, but in this investigation, they are not the area of interest. The color of the top of the bump is what matters, because it indicates whether the top lies within the narrow vertical range for successful bonding. Interpretation of the image is simplified by software that stretches the image of each solder bump vertically. If the solder bumps were imaged in their actual height, the gate in which the top should lie would be tiny and hard to see. Stretching each bump vertically does not change the measurement, it simply makes the results easier to interpret.

FIGURE 1 shows an acoustic side view image of a solder bump in its unstretched form, and the stretched form of its acoustic image. (Acoustic side views of internal features can be made by Sonoscan’s Q-BAMTM imaging mode, designed for non-destructive cross sectioning.) Even after the image is stretched, it may represent a vertical extent of only several microns. If bumps were imaged without vertical exaggeration, distinguishing accept from reject might be very difficult or even impossible. The amount of stretching needed for the bumps on a particular part type of BGAs, and the vertical extent of the gate that will yield the best results can typically be determined from previous experience with a BGA. Overall, what matters is not the precise configuration of the gate but ensuring that all bumps are very close to each other in height.

FIGURE 2 is the stretched 3D image of the solder bumps on one BGA before placement onto a PCB. The desired condition is that the top surface of the bump lie within the thin horizontal slice colored green in the image. FIGURE 3 is a magnified view of a small section of Fig. 2.

All the bumps in this BGA have tops that lie within the vertical “green” gate. There are no bumps toppled by other colors, a condition that would reveal that the bump might not bond to the substrate as well. The black areas in the figure are locations where no bump is present. BGAs like this are loaded into JEDEC-style trays and imaged in large quantities. Identification and removal of BGAs having one or more unsuitable bumps can be automated. The failure criteria are completely customizable depending on the level of tolerance a particular sample is held to.

FIGURE 4 is a small portion of the 3D image of a BGA where results were not quite so uniform. The desired color for the top of each bump here is red. As shown red is the top color on many of the bumps, especially in the left half of the image. But elsewhere there are bumps with pink, orange and other top colors. This is a BGA that may not make good contact with the PCB. Further down the assembly line this sample would likely experience immediate or early electrical failures due to attachment issues.

Location information can become useful to large scale production companies that are trying to understand their process better. If there are trends that suggest a specific location on the BGA is having a bump height problem, then there maybe something related to the process, handling, or materials being used that could be causing the issue. The measurement can be taken simultaneously while scanning in standard reflection mode. There is no addition in scan time or reduction in UPH to make this measurement.

3D imaging can also be used to depict strictly internal features. The operator sets two vertical values – an internal gate – to define the top and bottom of the desired depth measurement. This mode is known as profile mode imaging. When imaging in profile mode, only the echoes that occur within the depth of the gate are used for imaging. Signals outside of the gate are ignored. Because this is 3D imaging inside the part, the variation is measured relative to the top surface of the part.

3D acoustic imaging is useful for measuring the heights of bumps on BGAs, flip chips, and other devices. But it can also be used to image and quantify depth/ height variation of features within a particular sample. Measuring the distance of each of the thousands of x-y locations across the entire top surface of a tilted die can reveal how much of a threat to longevity the tilt is. It may even be helpful to stretch the image vertically to make so that the tilt could be easily seen to the human eye. Depending on the gate and depth chosen for a given profile mode image, it is possible to discern defects that occur at different height locations. This can be useful by showing that two similar looking defects may not be occurring at the exact same depth within the part. For example, you may have a void within the molding compound just a few microns before the lead frame. In standard reflection mode imaging, it would be impossible to determine if the defect occurred just before the lead (inclusion within the mold compound) or if the defect was a result of poor bonding directly to the lead frame. The is because standard reflection mode imaging only measures the amplitude of a given echo and not its location in time. Using profile mode, the depth location information is displayed using a color bar to depict the height infor- mation. In this way, defects that occur at different heights will also be assigned a different color value. This is the value of 3D acoustic imaging: mapping Time-Distance relationships at the surface or inter- nally for a given sample in a manner that is useful and easy to interpret.

How to tame the electromagnetic interference in the fabs and beyond

December 7, 2017

By Inna Skvortsova, SEMI

Electromagnetic interference (EMI) is an increasingly important topic across the global electronics manufacturing supply chain. Progressively smaller geometries of ICs, lower supply voltages, and higher data rates all make devices and processes more vulnerable to EMI. Electrical noise, EMI-induced signal generated by equipment, and factors such as power line transients affect manufacturing processes, from wafer handling to wire bonding to PCB assembly and test, causing millions of dollars in losses to the industry. Furthermore, conducted emission capable of causing electrical overstress (EOS) can damage sensitive semiconductor devices. Intel consistently names EOS as the “number one source of damage to IC components.” (Intel® Manufacturing Enabling Guide 2001, 2010, 2016).

While EMC (Electromagnetic Compatibility) standards, such as the European EMC Directive and FCC Testing and Certification, etc. provide limits on allowed emission levels of equipment, once the equipment is installed along with other tools, the EMI levels in actual operating environments can be substantially different and therefore impact the equipment operation, performance, and reliability. For example, (i) Occasional transients induce “extra” pulses in rotary feedback of the servo motor which in time contributes to robotic arm’s erroneous position eventually damaging the wafer; (ii) Combination of high-frequency noise from servo motors and switched mode power supplies in the tool creates difference in voltage between the bonding wire/funnel and the device which causes high current and eventual electrical overstress to the devices; (iii) Wafer probe test provides inconsistent results due to high level of EMI on the wafer chuck caused by a combination of several servo motors in the wafer handler. Field cases like these illustrate the gap between EMC test requirements and real-life EMI tolerance levels and its impact on semiconductor manufacturing and handling.

EMI on AC power lines

New standard, SEMI E176-1017, Guide to Assess and Minimize Electromagnetic Interference (EMI) in a Semiconductor Manufacturing Environment, developed by the NA Chapter of the Global Metrics Technical Committee bridges this gap. Targeted to IC manufacturers and anyone handling semiconductor devices, such as PCB assembly and integration of electronic devices, SEMI E176 is a practical guide as well as an educational document. SEMI E176 provides a concise summary of EMI origins, EMI propagation, measurement techniques and recommendations on mitigation of undesirable electromagnetic emission to enable equipment co-existence and proper operation as well as reduction of EOS in its intended usage environment. Specifically, E176 provides recommended levels for different types of EMI based on IC geometries.

“SEMI E176 is likely the only active Standard in the entire industry providing recommendations on both acceptable levels of EMI in manufacturing environments and the means of achieving and maintaining these numbers,” said Vladimir Kraz, co-Chair of the NA Metrics Technical Committee and president of OnFILTER, Inc. “E176 is also unique because it is not limited just to semiconductor manufacturing, but has application across other industries. Back-end assembly and test, as well as PCB assembly are just as affected by EMI and can benefit from SEMI E176 implementation as there are strong similarities between handling of semiconductor devices in IC manufacturing and in PCB assemblies and prevention of defects is often shared between IC and PCBA manufacturers.”

The newly published SEMI E176 and recently updated SEMI E33-0217, Guide for Semiconductor Manufacturing Equipment Electromagnetic Compatibility (EMC),provide complete documentation for establishing and maintaining low EMI levels in the manufacturing environment.

Undesirable emission has operational, liability and regulatory consequences. Taming it is a challenging task and requires a comprehensive approach that starts from proper system design practices and ends with developing EMI expertise in the field. The new SEMI 176 provides practical guidance on reducing EMI to the levels necessary for effective high yield semiconductor manufacturing today and in the future.

SEMI Standards development activities take place throughout the year in all major manufacturing regions. To get involved, join the SEMI International Standards Program at: www.semi.org/standardsmembership.

Smart management in the sub-fab improves safety, reliability, cost and yield

December 6, 2017

BY ANDREW CHAMBERS, Senior Product Manager, Edwards Ltd.

With the prospects of large 450mm wafers going nowhere, IC manufacturers are increasing efforts to maximize fabrication plants using 300mm and 200mm diameter silicon substrates. The number of 300mm wafer production-class fabs in operation worldwide is expected to increase each year between now and 2021 to reach 123 compared to 98 in 2016, according to the forecast in IC Insights’ Global Wafer Capacity 2017-2021 report.

Significant opportunities to improve safety, reliability and yield still remain in our industry, many of them to be found in the sub-fab, where the critical systems that supply vacuum and treat exhaust gases are to be found—out of sight and, too often, out of mind. Properly handling and removing noxious components in the exhaust flow clearly impacts the safety of fab personnel and the quality of the local environment. As for reliability, when the sub-fab fails the process is down. And yield—the yield of many tools depends directly on steady, high-quality vacuum. “Smart” management of sub-fab systems can improve safety, reliability, yield, and energy efficiency, all of which contribute directly to the bottom line.

For example, consider high-flow CVD processes, which are finding increasing application in high-volume production of 3D-NAND, DRAM and other devices. The process precursors and their decomposition products can present a flammability risk and, unless properly controlled, can condense as hazardous materials in process exhausts. Such condensation can cause a variety of operational problems, including process shut-downs when pipes become blocked, exhaust pipe fires when fluorine reacts with residual silicon compounds, and HF vapour releases when pipes are exposed to atmosphere during cleaning.

Several approaches may be used to address these concerns, alone or in combination. The entire exhaust assembly may be heated to maintain a thermal profile that eliminates conden- sation, though eliminating all cold spots can pose practical difficulties and constant monitoring is required. Exhaust gases may be diluted to mitigate flammability risks, but the cost of the additional diluting gas (N2) becomes prohibitive at high flows. The total cost of ownership for high dilution flows must
also include increased capital investment, operating cost and sub-fab space require- ments for additional abatement capacity.

A smart dilution strategy would continuously adjust the flow of dilution gas based on information from the process tool. Is flammable gas flowing? Is oxidant gas present? If the process gas is non-flammable, can dilution be eliminated entirely? When only a flammable gas is flowing, how much can dilution be relaxed while still maintaining the mixture below the lower flammability limit; or can it be allowed to exceed the LFL, since there is no concurrently flowing oxidant? When flammable gases flow concurrently with oxidizing gases, what dilution is required to keep the concentration of flammable gas below its LFL, with a sufficient safety margin to allow for fault scenarios? What is the best dilution for cleaning gases to optimize the safety and efficiency in their abatement? Answers to these questions and more can be found by analyzing information from the process tool and can be used in a smart dilution strategy to ensure safety, and maximize reliability and yield while minimizing cost.

Information from the process tool can also be used to control the operation of the abatement system. When only flammable gas is flowing with low or moderate dilution, the abatement system can be operated in a “low fire” mode, minimizing consumption of fuel, city water and process cooling water. When flammable and oxidizing gases flow concurrently and high dilution flow is used, the abatement can be switched into a “high fire” mode to ensure full destruction of the process chemicals.

Coupled with smart operation, smart system design can further improve safety, reliability and cost. Consider the problem of gas leaks. Leaks from process exhaust pipes can lead to fires, equipment damage and harm to sub-fab personnel. Local gas leak detectors can protect personnel but risk process shut-down and product loss. Rigorous leak checking proce- dures can reduce the risk of leaks following maintenance, but cannot prevent progressive seal degradation or leaks that occur during normal operation. A smart design integrates pumps, abatement and all connecting piping in a single unit, engineered for performance and safety and thoroughly tested at all stages of manufacturing and installation. Integration also permits exhaust integrity checking, double-containment, accurate and consistent exhaust temperature control, and tool-connected “smart” operation and provides single-vendor responsibility for maintenance and performance.

Opportunities for improvements abound, but taking advantage of them requires a smart approach based on broad experience and thorough understanding of semiconductor manufacturing processes.

Automotive and IoT will driveÂ IC growth through 2021

December 6, 2017

Integrated circuit sales for automotive systems and the Internet of Things are forecast to grow 70% faster than total IC revenues between 2016 and 2021, according to IC Insights’ new 2018 Integrated Circuit Market Drivers Report. ICs used in automobiles and other vehicles are forecast to generate worldwide sales of $42.9 billion in 2021 compared to $22.9 billion in 2016, while integrated circuit revenues for Internet of Things (IoT) functionality in a wide range of systems, sensors, and objects are expected to reach $34.2 billion in four years compared to $18.4 billion last year, says the new 358-page report.

Between 2016 and 2021, automotive and IoT IC sales are projected to rise by compound annual growth rates (CAGRs) of 13.4% and 13.2%, respectively, compared to 7.9% for the entire IC market, which is projected to reach $434.5 billion in four years versus $297.7 billion last year. As shown in Figure 1, strong five-year IC sales growth rates are also expected in medical electronics (a CAGR of 9.7% to $7.8 billion in 2021) and wearable systems (a CAGR of 9.0% to $4.9 billion).

Figure 1

Cellphone IC sales—the biggest end-use market application for integrated circuits, accounting for about 25% of the IC market’s total revenues—are expected to grow by a CAGR of 7.8% in the 2016-2021 period, reaching $105.6 billion in the final year of the new report’s forecast. Meanwhile, weak and negative IC sales growth rates are expected to continue in video game consoles (a CAGR of -1.9% to $9.7 billion in 2021) and tablet computers (a CAGR of -2.3% to 10.7 billion), according to the 2018 IC Market Drivers report.

Sharply higher average selling prices (ASPs) for DRAMs and NAND flash are playing a significant role in driving up dollar-sales volumes for ICs in cellphones and PCs (both desktop and notebook computers) in 2017. Cellphone IC sales are on pace to surge 24% this year to an estimated $89.7 billion, while PC integrated circuit dollar volume is expected to climb 17.6% to $69.0 billion. For both the cellphone and PC market segments, 2017 will be the strongest increase in IC sales since the 2010 recovery year from the 2009 downturn. The 2018 IC Market Drivers report’s forecast shows cellphone integrated circuit sales rising 8% to $97.3 billion next year and PC IC revenues growing 5% to $72.6 billion in 2018.

The new report estimates that automotive IC sales will rise 22% in 2017 to about $28.0 billion after increasing 11% in 2016. Automotive IC sales are forecast to increase 16% in 2018 to $32.4 billion. Meanwhile, IoT-related integrated circuit sales are on pace to grow 14% in 2017 to an estimated $14.5 billion after increasing about 18% in 2016. In 2018, integrated circuit sales for Internet of Things end-use applications are expected to rise 16% to about $16.8 billion, according to the 2018 edition of the IC Market Drivers report.

Leti integrates hybrid III-V silicon lasers on 200mm wafers using standard CMOS process

December 6, 2017

Leti, a research institute of CEA Tech, has integrated hybrid III-V silicon lasers on 200mm wafers using standard CMOS process flow. This breakthrough shows the way to transitioning away from 100mm wafers and a process based on bulk III-V technology that requires contacts with noble metals and lift-off based patterning.

The project, carried out in the framework of the IRT Nanoelec program, which is headed by Leti, demonstrated that the hybrid device’s performance is comparable to the reference device fabricated with the current process on 100mm wafers. The fabrication flow is fully planar and compatible with large-scale integration on silicon-photonic circuits.

The results were reported Dec. 5 at IEDM 2017 in a paper titled “Hybrid III-V/Si DFB Laser Integration on a 200mm Fully CMOS-compatible Silicon Photonics Platform”.

CMOS compatibility with silicon photonics lowers fabrication costs, and provides access to mature and large-scale facilities, which enables packaging compatibility with CMOS driving circuits.

“Silicon-photonic technologies are becoming more mature, but the main limitation of these platforms is the lack of an integrated light source,” said Bertrand Szelag, a co-author of the paper. “This project showed that a laser can be integrated on a mature silicon-photonic platform with a modular approach that does not compromise baseline process performances. We demonstrated that the entire process can be done in a standard CMOS fabrication line with conventional process and materials, and that it is possible to integrate all the photonic building blocks at large scale.”

The integration required managing a thick silicon film, typically 500nm thick, for the hybrid laser, and a thinner one, typically 300nm, for the baseline silicon-photonic platform. This required locally thickening the silicon by adding 200nm of amorphous silicon via a damascene process, which presents the advantage of leaving a flat surface favorable for bonding III-V silicon. The laser can be integrated on a mature silicon photonic platform with a modular approach that does not compromise the baseline process performance.

The novelty of the approach also included using innovative laser electrical contacts that do not contain any noble metals, such as gold. The contacts also prohibit integration lift-off-based processes. Nickel-based metallization was used with an integration technique similar to a CMOS transistor technique, in which tungsten plugs connect the device to the routing metal lines.

Next steps include integrating the laser with active silicon-photonic devices, e.g. a modulator and photodiode with several interconnect metal levels in a planarized backend. Finally, III-V die bonding will replace III-V wafer bonding in order to process lasers on the entire silicon wafer.

Tilted scanning electron microscopy view of the III-V/Si DFB laser after the IIIV patterning steps.

Laser spectrum at 160 mA injection currents

The quantum waltz of electrons hints at the next generation of chips

December 6, 2017

A group of spintronics researchers at EPFL is using new materials to reveal more of the many capabilities of electrons. The field of spintronics seeks to tap the quantum properties of “spin,” the term often used to describe one of the fundamental properties of elementary particles – in this case, electrons. This is among the most cutting-edge areas of research in electronics today.

Researchers working in the Laboratory of Nanoscale Electronics and Structures (LANES), which is run by Professor Andras Kis, were able to quantify these quantum properties for a category of two-dimensional semiconductors called transition metal dichalcogenides, or TMDCs. Their research projects, which were published recently in ACS Nano and today in Nature Communications, confirm that materials like graphene (C), molybdenite (MoS2) and tungsten diselenide (WSe2) offer, either alone or by combining some of their characteristics, new perspectives for the field of electronics – perspectives that could ultimately lead to smaller chips that generate less heat.

“With the methods we’ve recently developed, we’ve shown that it is possible to access the spin in these TMDC materials, quantify it and use it to introduce new functionalities,” says Kis.

This all takes place at an extremely small scale. In order to access these quantum properties, the researchers must work with high quality materials. “If we want to examine certain characteristics of electrons, including their energy, we need to be able to watch them move over relatively long distances without there being too much dispersion or disruption,” explains Kis.

In the form of waves

The researchers’ method allows them to obtain samples of sufficient quality both to observe how electrons move around in the form of waves and to quantify their energy.

But the LANES team was also able to access another quantum property. Spins of electrons and holes in this type of a 2D semiconductor can be in one of two states, which are conventionally described as being oriented upward – spin up – or downward – spin down. Their energy will be slightly different in each of these two states. That’s called spin splitting, and the EPFL researchers have measured it for the first time for electrons in TMDC materials. In the second publication, the researchers wrote about how they used the spin splitting in a TMDC in order to introduce polarized spin currents in graphene without using a magnetic field.

These discoveries are a step forward for the emerging field of spintronics and make it increasingly likely that a different property of charge carriers – i.e. spin, in addition to the electrical charge – will play a role in tomorrow’s electronic devices.

Surface preparation technology provides pristine and stable hydrogen passivated semiconductor surfaces

December 6, 2017

A new technology enables dramatically lower thermal budget capability that is enabling to thermal processes like epitaxy, CVD and diffusion, without any semiconductor material consumption.

BY ROBERT PAGLIARO, RP Innovative Engineering Solutions, LLC, Mesa, AZ

As semiconductor based electronic devices have become smaller, faster, smarter, 3-dimensional, and multi-functional the methods and materials required to fabricate them demand novel approaches to be developed and implemented in the device manufacturing facilities. Amongst the most challenging requirements are the need to lower the thermal budgets of the front end thermal processes and to minimize the semiconductor material consumption that comes with the conventional oxidizing (hydrogen peroxide and ozone based chemistries) wet cleaning processes chemistries such as APM, HPM, SPM and SOM.

A novel wet surface preparation method that removes existing surface contamination and native oxide from semiconductor surfaces and then passivates them with a pristine and stable hydrogen passivated surface has been developed and commercialized by APET Co, Ltd. in a system called the TeraDox. This patented technology enables dramatically lower thermal budget capability that is enabling to thermal processes like epitaxy, CVD and diffusion, without any semiconductor material consumption.

The TeraDox system is an enhanced version of the APET FRD (HF etching, Rinse and Dry). The name TeraDox implies the ability to provide a process chemistry with < 1 ppb impurities, particularly dissolved oxygen, which allows for producing pristine and stable H-passivated semiconductor surfaces. Dilute HF and HCl (dHF and dHCl) are the etching chemistries used for removing the native and chemical oxides from Si, SiGe and Ge surfaces. The TeraDox system has a single vessel wet processor and a wafer transfer/drying hood that allows for a segue between the load, chemical fill, etch, insitu-rinse, dry and unload steps of the process sequence, while keeping the process chemistry and the wafers in a continuous ambient of ultra- pure N2. This equipment and process design eliminate the exposure of the wafers to air and minimizes gas perme- ation throughout the entire oxide removal and H-passiv- ation process sequence. These are all critical elements to achieving the best surface quality results. While there are a variety of important parameters towards achieving a pristine and stable H-passivated surface one of the most enabling ingredients to the APET TeraDox process and equipment IP is the PPT level degassing capability for the UPW and aqueous chemicals used in the H-passivation process. The unique UPW and chemical degassing apparatus require an optimized hardware configuration with membrane contactors and facilities used for the vacuum + UHP N2 sweep gas to achieve a DO degassing efficiency > 99.999%. This ultra-high degassing efficiency allows for a Dissolved Oxygen (DO) concen- tration capability of < 100 ppt.

It has been well proven and documented by multiple world-renowned surface scientists [1,2,3] since the late 1980s that the level of dissolved oxygen (DO), as well as other dissolved impurities (such as CO2, TOC, silica and N2), has a direct impact on the efficiency of H-passivation and the native oxide (initial and changing thickness vs. queue time) that follows the removal of native and chemical oxides from semicon- ductor surfaces. Queue time (Q-time) is the amount of time that the H-passivated wafer are exposed to air before being placed in an inert environment for the subsequent process step (epi, poly silicon, metal, ion implantation etc.). It can be seen in FIGURE 1 how native oxide regrowth occurs after HF treatment in air and UPW vs. exposure time [1].

A similar DO vs. surface oxide and carbon relationship is also verified using encapsulated SIMS. This method uses dynamic SIMS to measure the amount of O, C that are trapped at the epi layer/silicon wafer interface. This has been a widely used characterization method to assess a pre-low temperature epi surface prepa- ration process’ hydrogen surface passivation quality since the early 90s. The typical epi cap is ~80-150nm and is deposited using a 650°C SiH4 source deposition process. The objective is to be able to minimize the thermal budget of the pre-deposition bake step which is required to remove any surface oxides and organics to allow perfect epitaxial deposition with no contami- nants or defects at the interface.

FIGURE 2 demonstrates how the encapsulated SIMS interface O (areal oxide density, AOD) using a 650°C SiH4 no bake Si deposition process is strongly dependent on the DO concentration. Three samples are depicted with different surface preparation conditions, a reference wafer with no surface preparation, a wafer dHF wet processedwith the UPW DO ~ 1ppb, and a wafer dHF wet processed with the DO ~0.1 ppb.

It can be seen in FIGURE 3 how applying a 700C/80T/60s bake before a 650C Si deposition process with the UPW DO at 0.1ppb yields non-detectable O and C. This SIMS data info is relatively old (2010) but is still good for reference. The current APET TeraDox wet process capability can provide non-detectable O and C without a bake before the 650°C Si deposition process.

As mentioned earlier, undesirable native oxide thickness increases with queue time on H-passivated Si, SiGe and Ge surfaces. So, it is important to minimize the Q-time between the H-passivation process and the subsequent process step, but the quality and stability of the H-passivation does need to accommodate practical queue times in a manufacturing environment. The H-passivation from the APET TeraDox process has proven to be stable enough for up to at least 8-hour Q-times for most low temperature process applications, which makes it suitable for most semiconductor device manufacturing facilities.

Aside from the low surface oxygen benefit from having ultra-low DO in this process there are other very important benefits to this as well. Having ultra-low DO prevents water marks, microroughness (faceting), bacterial contamination and material consumption. If there is no DO in the UPW or the etching chemistry then there is no competing mechanism to simultaneously oxidize and etch the semiconductor material during the oxide etch and insitu-rinse steps. If the surface is being oxidized/etched then orientation selective faceting will occur. Faceting leads to gener- ation a mix of mono-, di- and tri- hydride terminations on the different orientations of the semiconductor surface. An example is silicon (100), which if it is kept atomically smooth after the oxide is removed by HF, the surface will be dominated by di-hydride terminations. If the surface is faceted it will contain lower energy mono-hydride terminations. Higher energy hydride bonds lead to better surface stability while the lower energy hydride bonds make the surface less stable and will re-oxidize faster with Q-time.

So in general, the pristineness and the atomic smoothness of the semiconductor surface are what dictates the quality and stability of the H-passivating surface preparation process.

While the TeraDox process performance has continued to improve with the new innovations, the capabilities have surpassed the detection limits of conven- tional measurement methods like encapsulated SIMS characterization. Encapsulated SIMS also has a lot of drawbacks and limitations which make it an impractical process monitoring method in manufacturing facil- ities. The need to have a more sensitive measurement method that can measure “as processed” surfaces in a fast, real time and non-destructive manner had become an urgent requirement.

There are a variety of very good electrical and optical measurement methods that have been in use for many years, but most of them do not provide surface specific information directly. Surface parameters such as surface recombination velocity and lifetime (SRV and Ts) can be calculated relatively accurately using multiple step procedures by measurement methods such as uPCD, QSS-PC, PL and SPV. SRV (surface recombination velocity) and Ts (surface recombination lifetime) are extremely sensitive to surface contamination such as C, O metals and dopants as well as micro- roughness. This diverse sensitivity make it ideal for assessing surface preparation methods.

Until recently, only one measurement technique has been found that can measure the SRV and Teff (effective lifetime) of the surface directly and quickly on as processed H-passivated wafers. While doing a lot of research for the ideal measurement method to pair with the APET TeraDox H-passivation process, it was discovered that an enhanced version of the CADIPT department at the University of Toronto’s PCR-LIC technology, called Quantitative Lock-in Carrierog- raphy and Imaging (Q-LIC), could have the unique and enabling capabilities needed for this application. After completing an array of screening and optimization testing over the course of 8 months, the results have validated Q-LIC as an ideal measurement method for “as processed” H-passivated surfaces. In FIGURE 4, the plot demonstrates the SRV vs Q-time for four different wet cleans and an unprocessed control. The data shows strong evidence of the differentiation between different H-passivation methods (process and equipment), the level of DO in the wet process chemistry, and the dynamically changing surface state over time.

FIGURE 4. Q-LIC SRV measurements vs Q-time for four different HF last wet processes.

APET currently has five patents, related to this technology, integrated on the commercially available TeraDox wet process equipment, four of which include the use of vacuum/N2 sweep degassing with membrane contactors for both the UPW and chemical degassing.

The UPW degassing is done in a separate stand-alone module (called the APET Dox unit) that treats up to 60 lpm of UPW before going to the main unit. All Dox units are guaranteed to have DO < 1 ppb, but all of the units in use to date achieve < 200 ppt. The most recently installed Dox unit system has a base DO level of ~30-40 ppt. Aside from the importance of PPT level degassing of the UPW much attention has also been given towards the design and materials used in the entire TeraDox system to prevent gas permeation into the UPW supply and the process chemistry to achieve optimum H-passivation. The most recent TeraDox related patent that was issued to APET was for chemical degassing. The degassing of the HF and HCl are typically overlooked in this application. Typically, HF comes in ~48% and HCl in ~37% concentrations with the balance of these supplied mixtures is in DO saturated water. So even diluted etching chemistries of up to 400 (UPW) :1 (chemical) ratios will typically still produce a composite DO of > 3ppb in the process vessel, even if the UPW supply is degassed to 0 ppt. Having the unique chemical degassing capability to < 1ppb DO significant improves the overall performance of the H-passivation process. The chemical degassing apparatus is integrated into the HF and HCl chemical delivery lines inside the TeraDox system’s main unit.

In summary, APET has developed and commercialized a unique and enabling wet surface preparation technology, the TeraDox process and equipment, that can produce pristine and stable hydrogen passivated semiconductor surfaces. While there are several critical factors and innovations that enable the TeraDox’s unique process performance capabilities, the fully integrated “dry in/dry out” system design and the unique PPT level degassing of the process chemistries are the most facili- tating features on the TeraDox system.

Acknowledgement

A special thanks to Dr. Andreas Mandelis and his staff at the University of Toronto for their support in optimizing their Q-LIC system to provide data for this paper as well as demonstrating a suitable measurement method for the “as processed” H-passivation application.

References

1. M. Morita et al, J. Appl. Phys. 88 (3), 1 (1990)
2. A. Philipossian, J. Electrochem. Soc. 139 No. 10, 2956 (1992)
3. F. H. Li, M. K. Balazs, and S. Anderson, J. Electrochem. Soc. 152,
G669 (2005)

Global semiconductor sales increase 21.9%Â year-to-year in October

December 5, 2017

The Semiconductor Industry Association (SIA) today announced worldwide sales of semiconductors reached $37.1 billion for the month of October 2017, an increase of 21.9 percent from the October 2016 total of $30.4 billion and 3.2 percent more than last month’s total of $36.0 billion. October marked the global industry’s largest-ever monthly sales total. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average. Additionally, the latest WSTS industry forecast was revised upward and now projects annual global market growth of 20.6 percent in 2017 and 7.0 percent in 2018.

“The global semiconductor market continued to grow impressively in October, with sales surpassing the industry’s highest-ever monthly total and moving closer to topping $400 billion for 2017,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Market growth continues to be driven in part by high demand for memory products, but combined sales of all other semiconductor products were up substantially as well, showing the breadth of the market’s strength this year.”

Regionally, year-to-year sales increased in the Americas (40.9 percent), Europe (19.5 percent), China (19.1 percent), Asia Pacific/All Other (16.3 percent), and Japan (10.7 percent). Compared with last month, sales were up more modestly across all regions: the Americas (6.8 percent), China (2.6 percent), Europe (2.6 percent), Japan (1.8 percent), and Asia Pacific/All Other (1.5 percent).

Additionally, SIA today endorsed the WSTS Autumn 2017 global semiconductor sales forecast, which projects the industry’s worldwide sales will be $408.7 billion in 2017. This would mark the industry’s highest-ever annual sales, its first time topping $400 billion, and a 20.6 percent increase from the 2016 sales total. WSTS projects double-digit year-to-year increases across all regional markets for 2017: the Americas (31.9 percent), Asia Pacific (18.9 percent), Europe (16.3 percent), and Japan (12.6 percent). Beyond 2017, growth in the semiconductor market is expected to moderate across all regions. WSTS tabulates its semi-annual industry forecast by convening an extensive group of global semiconductor companies that provide accurate and timely indicators of semiconductor trends.

To find out how to purchase the WSTS Subscription Package, which includes comprehensive monthly semiconductor sales data and detailed WSTS Forecasts, please visit http://www.semiconductors.org/industry_statistics/wsts_subscription_package/. For detailed data on the global and U.S. semiconductor industry and market, consider purchasing the 2017 SIA Databook: https://www.semiconductors.org/forms/sia_databook/.

Oct 2017
Billions
Month-to-Month Sales
Market	Last Month	Current Month	% Change
Americas	7.99	8.54	6.8%
Europe	3.28	3.37	2.6%
Japan	3.14	3.20	1.8%
China	11.36	11.65	2.6%
Asia Pacific/All Other	10.18	10.33	1.5%
Total	35.95	37.09	3.2%

Year-to-Year Sales
Market	Last Year	Current Month	% Change
Americas	6.06	8.54	40.9%
Europe	2.82	3.37	19.5%
Japan	2.89	3.20	10.7%
China	9.78	11.65	19.1%
Asia Pacific/All Other	8.88	10.33	16.3%
Total	30.43	37.09	21.9%

Three-Month-Moving Average Sales
Market	May/Jun/Jul	Aug/Sep/Oct	% Change
Americas	6.94	8.54	23.0%
Europe	3.20	3.37	5.1%
Japan	3.04	3.20	5.2%
China	10.68	11.65	9.1%
Asia Pacific/All Other	9.77	10.33	5.8%
Total	33.63	37.09	10.3%

Solutions for controlling resin bleed out

December 5, 2017

The hows and whys of resin bleed-out (RBO) are discussed, as well as the impact it makes and how to control it.

BY RONGWEI ZHANG, ABRAM CASTRO and YONG LIN, Semiconductor Packaging, Texas Instruments Inc., Dallas, TX

Die attach pastes, which consist of resin, curing agent, catalyst, filler and additives, have been extensively used to attach die onto lead frames in various electronic packages such as small outline integrated circuit (SOIC), thin-shrink small outline package (TSSOP), quad flat package (QFP) and quad-flat no-lead (QFN). One of the issues commonly encountered during package assembly is resin bleed-out (RBO), or epoxy bleed out (EBO). RBO is the separation of some formulation ingredients in the paste from the bulk paste (see FIGURE 1). Depending on die attach paste formulations and lead frame surface chemistry and morphology, bleeding ingredients can be solvents, reactive diluents, low-molecular-weight resins, catalysts, and additives like adhesion promoter. Resin bleed out tends to occur on high energy surfaces such as metal lead frames without any organic coating. In particular, if plasma cleaning is utilized to remove the contaminants prior to assembly, the bleeding issue may become more pronounced due to the increase in surface energy. Bleed-out can occur once die attach pastes are dispensed on to lead frames or during thermal curing. As microelectronics continue to move towards smaller form factor, higher reliability and higher performance, control of RBO becomes increasingly critical for packages where there is a very little clearance between die and die pad edge, or between one die and another in multi-chip modules (MCMs).

How resin bleed-out occurs

When die attach paste is dispensed onto a solid surface like lead frame surface, the paste will typically wet the surface partially. The adhesive force between die attach paste and lead frame surface causes the paste to spread while the cohesive force within the bulk paste will hold the ingredients together and avoid contact with a lead frame surface. The adhesive and cohesive forces are the intermolecular forces such as hydrogen bonding and Van der Waals forces. So the degree of wetting will depend on the balance between adhesive force and cohesive force. Bleed-out occurs when the adhesive force of some formulation ingredients to the substrate is stronger than the cohesive force within the paste. The driving force for bleed out is to minimize the surface energy of the substrate by wetting.

Impact of resin bleed-out

Resin bleed-out can cause several issues if it is not well controlled.

• If the formulation ingredients bleed from the periphery of the die attach pastes and covers the wire bonding area, then issues like non-stick on pad (NSOP) and weak wire bond can occur. It can also be an issue if bleeding occurs from the die attach fillet along die edge to the die top, contaminating the bond pad on die top surface [1].

• Resin bleed-out may affect the adhesion of mold compound to die pad or mold compound to die top surface, both of which can lead to delamination. In particular, die top delamination is strictly not allowed in wire-bonded packages because it can cause the ball bond to be mechanically lifted, thereby leading to electrical failures during temperature cycling [2].

• As the formulation ingredients bleed out of the bulk paste, the composition of die attach paste under die may change accordingly. This can impact the adhesion of die attach to lead frame adversely, leading to an adhesive failure [3].

Influence of surface roughness

There are many factors that can cause resin bleed-out, such as low surface tension of die attach pastes, high surface energy of metal lead frames, surface contami- nation, surface porosity and surface roughness. Here we will focus on the impact of surface roughness, which is critical to achieve high package reliability. Two die attach pastes were dispensed onto three lead frames with different surface roughness. The surface roughness of these three lead frames was characterized by Atomic Force Microscopy (AFM) using the roughness average (Ra) and the roughness ratio (r) (FIGURE 2). The roughness average (Ra) represents the arithmetic average of the deviations from the center plane. The roughness ratio is the ratio between the actual 3-D surface area calculated by AFM and the flat surface. The 3D morphologies of lead frames are shown in FIGURE 3. It was found that (a) there is a good correlation between the roughness ratio and resin bleed-out. As the surface roughness ratio increases, the bleeding becomes increasingly worse; (b) LF1 and LF2 have almost same Ra, but the bleeding performance of DA3 and DA4 are different. This indicates that the roughness average is not a good index for RBO; (c) DA4 is more resistant to bleed out than DA3.

The relationship between surface roughness and the wettability has been described by Young equation (Equ. 1) and Wenzel equation (Equ. 2).

cos0y=(YS-YSL)/YL (1)0
cosöm=rcos0y (2)

Where Ys, YL, YSL are surface tensions of the solid, liquid and interfacial tension between die attach paste and lead frame, respectively; 0y is the Young contact angle, 0m is the measured contact angle, and r is the roughness ratio. As the surface roughness increases, the better the wetting, and the worse the bleed-out if the contact angle is < 90o [4]. This is the case for die attach paste on a metal surface without anti-EBO coating.

Approaches to control resin bleed out

There are several approaches to control or eliminate resin bleed-out. These approaches include modifying formulation by selecting appropriate anti-EBO, using die attach film (DAF)/B-stage epoxy, controlling surface roughness, creating mechanical barrier, and lowering the surface energy of lead frames by surface coating.

• Modifying formulations. Generally, anti-bleeding agents are added to die attach pastes to reduce or eliminate RBO. Different anti-bleeding agents may have different working mechanisms. Some anti- bleeding agents are added to enhance the cohesiveness of the pastes while others are added to form a thin layer with a surface energy lower than the pastes themselves on a lead frame surface [5]. Therefore, tailoring die attach adhesives with appropriate anti-bleeding agents is critical to prevent RBO on different types of lead frames, while maintaining high adhesion to metal lead frames to achieve high reliability.

• Die Attach Film/B-stage Epoxy. The simplest and most effective way to eliminate RBO is to use die attach films or B-stage materials. However, there are limitations associated with this approach. These can include high material cost and capital investment, difficulty to achieve high adhesion and thus high reliability, and limited thermal performance of these materials.

• Mechanical barriers. In some cases, grooves on lead frames are designed in between die attach area and wire bond area to reduce resin bleed-out, as shown in FIGURE 4. This is a simple and cost-effective process. However, this approach may not work well if the bleeding is severe. Similarly, some low surface energy insulating film around a chip can be printed to confine the un-cure pastes to the space defined by the printed pattern [5].

• Vacuum baking. Vacuum baking of ceramic substrates with gold or other metal surfaces has been reported to reduce bleed-out. Several mechanisms were proposed: (a) through removal of polar surface contaminant, which promotes bleed-out of lighter organic resin by dipole attraction or chemical reaction [6]; (b) through reducing the surface energy of the plating surface by the formation of Ni2O3 [7]; (c) through producing a coating of hydrocarbon by oil back streaming toreduce the surface energy [8]. The method is not recommended either due to lack of controllability or due to the detrimental effect on wire bonding quality [7]. A more controlled method to reduce or eliminate RBO is to treat the surface with known chemicals and controlled processes, as discussed below.

• Low surface energy coating. Roughened lead frames have been utilized to enhance package reliability, particularly to meet Automotive Grade 0 requirements or beyond, as they increase surface contact area and enhance mechanical interlocking. As shown in Fig. 2, a small increase in roughness can result in a severe bleed-out. Therefore, increasing surface roughness will promote bleed-out if there is no anti-EBO on the surface. According to Young’s equation, decreasing surface energy will increase the contact angle, i.e. decreasing the wetting of the surface. Therefore, in roughened lead frame manufacturing, a solution of low surface energy material is used to treat roughened lead frames to lower their surface energy to reduce or eliminate RBO. Alternatively, a thin layer of film can be deposited onto the assembly surface by gas plasma technology to modify the surface energy [9]. FIGURE 5 shows water contact angles of lead frames with or without anti-EBO treatment. The anti-EBO coating will increase the contact angle on standard lead frame as explained by Young’s equation. Compared with standard lead frames, roughened lead frames have an increasing roughness and the anti-EBO coating on roughened lead frames further increases contact angle significantly. This can be explained by Wenzel equation, which demonstrates that adding surface roughness will increase surface hydrophobicity if the surface is chemically hydrophobic. In addition, Fig. 5 shows the resin bleed-out performances of a die attach paste (DA2) on these three types of lead frames. Bleed out was observed on the standard lead frame without anti-EBO, but there was no bleeding on both standard and roughened lead frame with anti-EBO coating. The low surface energy anti-EBO coating eliminates resin bleed out.

Summary

This article provides an understanding of how bleeding occurs, the impact of bleeding, and methods to control bleeding. Bleeding is the result of the interaction between die attach pastes and metal lead frames. In particular, we studied the influence of surface roughness on RBO of different die attach materials, and found that there is a good correlation between the roughness ratio and bleed-out performance. Reducing the surface roughness will reduce or eliminate RBO. It is noteworthy that there is a line between reducing roughness to achieve no RBO and increasing roughness to ensure excellent delamination performance for lead frames without Anti-EBO. In terms of die attach pastes, the most effective way to control RBO seems to be the surface coating with anti-RBO without affecting other performances like delamination, or combining this method with others to provide an even better solution.

References

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2. R. W. Zhang, Y. Lin, A. Castro, “Solving delamination in lead frame- based packages”, Chip scale review, 2015, pp. 44-48.
3. S. Kanagavel, D. Hart, “Optimization of die attach to surface-enhanced lead frames for MSL-1 performance of QFN packages”, Chip scale review, 2017, pp. 35-38.
4. J.-C. Hsiung, R.A. Pearson, T.B. Lloyd, “A surface energy approach for analyzing die attach adhesive resin bleed,” J. of Adhesion Science and Technology, 2003, 17, No. 1, pp. 1-13.
5. H. Schonhorn, L. H. Sharpe, “Liquids with reduced spreading tendency”, US Patent 4,483,898.
6. J. Ireland, “Epoxy bleedout in ceramic chip carriers”, Int. J Hybrid Microelectron., 1982, 5, pp. 1-4.
7. M. R. Marks, J. A. Thompson, R. Gopalakrishnan, “An experimental study of die attach polymer bleedout in ceramic packages”, Thin Solid Film, 1994, 252, pp. 54-60.
8. N. Tan, K. H. H. Lim, B. Chin, A. J. Bourdillon, “Engineering surface in ceramic pin grid array packaging to inhibit epoxy bleeding”, The Hewlett-Packard Journal, 1998, pp. 81-89.
9. M. Burmeister, “Elimination of epoxy resin bleed through thin film plasma deposition”, Proceeding of the 36th international IMAPS conference, Boston, MA, 2003, pp. 780-785.