Yearly Archives: 2017

A new illumination technology compares favorably to conventional bright field illumination.

BY GURVINDER SINGH, Director, Product Management, Rudolph Technologies, Inc., Wilmington, MA

A new optical technique can reveal defects and contaminants that escape conventional inspection technologies in many advanced packaging applications. As wafer level packaging (WLP), and especially fan-out wafer and panel level packaging (FOWLP/FOPLP), gains broader accep- tance, certain classes of defects that are characteristic of these processes present significant challenges to standard optical inspection tools. A new optical technology demonstrates increased sensitivity to transparent defects, such as residual dielectric films and photoresist, which are only marginally visible with conventional tools. At the same time, it is less sensitive to nuisance defects, such as those caused by the varying contrast and texture of grains in metal films, that should correctly be ignored.

Challenges in advanced packaging applications

Advanced packaging processes often involve the use of front-end-like technologies in back-end applications. Fan-out packaging is no exception, and, not surpris- ingly, it is following a similar development path, with increasing circuit complexity accompanied by shrinking circuit geometries. Redistribution layer (RDL) line widths, which were around 20μm in early implementations, will soon reach 2μm and are unlikely to stop there. Just as front-end processes placed increasing emphasis on enhanced process monitoring and control, advanced packaging processes will be forced to include more and better inspection and metrology capability at critical steps to maintain control and improve yields.

Advanced packaging processes, such as fan-out, face unique challenges that, for inspection systems, result in overcounting nuisance defects and undercounting yield-robbing critical defects. These advanced packaging techniques make extensive use of metal and organic polymers. Layers of metal are used to define conductive paths and organic polymer dielectric materials are used to provide insulation between conductors and planar surfaces between the layers. Dark field and bright field inspection results often include tens of thousands of nuisance defects. These occur because the inspection algorithms are designed to find random aberrations in highly repeatable patterns and the variable grain patterns of metal conductors appear as defects when are not. If not excluded, their large numbers can quickly overwhelm the real defects. Metal grain features can be as large as 50μm, much larger than RDL lines, which are currently as small as 2μm, and likely to reach 1μm in the near future.

Another class of defects that has proven difficult for conventional optical inspection techniques is caused by the presence of organic residues left after etching and descumming operations. They are hard to find because these materials tend to be transparent at visible wavelengths, yielding little signal in bright field and dark field inspection. They can be especially troublesome when they occur on contacts such as bumps and pillars. The new illumination method effectively eliminates nuisance noise from metal surface textures and enhances signal strength from organic defects.

ClearfindTM technology

The results presented here were all acquired using a FireflyTM inspection system (Rudolph Technologies) that incorpo- rates the new Clearfind (CF) illumination technology1. The new method takes advantage of the fact that many organic polymers exhibit distinctive optical properties that are not present in metals, silicon or other common inorganic materials used in semiconductor manufacturing. These properties tend to be unique to organic molecules displaying a high degree of conjugation, such as polycyclic aromatic hydrocarbons, and in linear or branched chain organic polymers with multiple regularly interspersed pi-bonds. This phenomenon results in the generation of a readily detectable, high color-contrast signal when the feature is appropriately illuminated against a metallic or other inorganic surface. The emission tends to be anisotropic and therefore less sensitive to surface topography that could potentially direct most ordinary bright field or dark field reflected light away from the detector. This results in increased sensitivity to organic residues and reduced sensitivity to interference from surrounding features. The method has the additional advantage of being relatively insensitive to signal variations caused by metal grains. FIGURE 1 presents a simplified illustration comparing the new technology to traditional white light inspection.

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The light source for the new technology is laser based, rather than the broadband source typically used in white light inspection systems. Thus, the light output is more stable in terms of both spectral range and output power. Autofocusing of the samples is accomplished using a patented high speed, near infrared-based laser triangulation system that maintains a constant distance between the imaging optics and the area being scanned. Images are acquired at high speed with a high-resolution camera. The result images compared in this article using bright field, dark field and CF technology were all acquired on the same inspection platform using different illumination techniques.

Through Silicon Via (TSV)

The sample is a 300mm silicon wafer with revealed TSV pillars2. TSV nail diameter is about 8μm and the distance between TSVs is about 56μm. The TSVs are on the backside of the wafer and the front side of the wafer is attached to a carrier.

In FIGURE 2a, the top shows a bright field image of two TSVs. The TSV on the left, circled in red, is covered with unetched organic residue and the TSV on the right, circled in green, is completely exposed. In the bright field image both TSVs look good and the residue is not visible. The images at the bottom left of figure 2 were acquired with CF technology and show the same TSVs. The TSV on the left, circled in red, has a bright blob while the one on the right, circled in green, is completely dark. The organic residue remaining on the left TSV now emits a readily detectable signal.

FIGURE 2b shows the inspection result from the full TSV wafer. The dots on the wafer map represent defect locations. There is a heavy concentration of organic residue on TSVs on the right side of the wafer. Metal pads approximately 35μm in diameter will be placed on top of the TSVs. Any organic residue between the TSV and the pad can cause deplanarization, which may result in connectivity issues when the die is stacked together. In addition, organic residue can increase the resistance of the contact when the die is stacked. If the defects are found before the next process step the wafer can be reworked.

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Under Bump Metal (UBM)

The sample is a 300mm wafer with RDL and under bump metallization (UBM). The UBM pads are about 50μm wide. In FIGURE 3a, the bright field image of two UBM pads shows the left pad is completely exposed and the right pad is covered with unetched organic film. However, the film is transparent and both pads look good in this image. Note the random metal texture visible in the bright field image, which adds noise and makes sensitive inspection for small defects more difficult. The image at lower left, acquired with CF technology, shows the same pads. The left pad, with no residue, appears black. The right pad, covered by residue, is significantly brighter. Also note that the metal texture seen in the bright field image with absent in CF illumination, permitting sensitive inspection for defects down to the pixel level.

FIGURE 3b shows a map of the full wafer where there is a heavy concentration of defects on UBM pads near the edge of the wafer. As in the TSV example, residue remaining on the UBM pads can cause increased resistance or loss of connectivity to a bump deposited on the pad. Bumps deposited on the residue are higher than normal bumps, leading to loss of coplanarity and connectivity issues. If the problem is found before starting the bump process, the wafer can be reworked and the residues removed.

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Redistribution Layer (RDL)

The sample is a 300mm molding compound wafer for fan-out packaging. FIGURE 4a shows a bright field image that includes a UBM pad and several RDL lines. The middle image shows the same area viewed with the new illumination technology. In the bright field image, the metal of the UBM pad and the RDL lines is very similar to the underlying metal visible through an interposed transparent film. The texture and graininess of the metals add noise to the image, increasing the difficulty of detecting small defects. Inspection with bright field illumination resulted in high nuisance defect counts without finding real process issues on the wafer. In FIGURE 4b, the top surface metal features, RDL and UBM, stand out against the background of the transparent film, while the underlying metal features are barely visible. FIGURE 4c shows a full wafer map acquired using CF technology and reveals a rectangular pattern that corresponds to the reticle of the lithography tool. The rectangular pattern was not visible in the bright field wafer map.

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FIGURE 5 shows additional RDL inspection results on the same wafer. CF technology revealed thinner lines toward the lower left corner of the reticle pattern. Ultimately, it was determined that these thinner lines were caused by a defect in the condenser lens of the lithography tool. The improved contrast between the first layer metal features in the underlying organic film, and the reduced noise, permitted more accurate and sensitive measurements using the new illumination technology. A bright field inspection of 20 wafers containing the same defect did not detect any thinner lines.

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Photoresist

The sample is a 300mm patterned silicon wafer from a large memory manufacturer3. It contains die approximately 11.7mm x 7.6mm in size, and containing arrays of about 9,000 metal pillars, each pillar approximately 22μm in diameter. The customer was interested to know if the new illumination technology would find defects not found by bright field inspection. FIGURE 6a shows a wafer map overlaying bright field defects (blue triangles) and CF defects (green triangles). In both cases the defects appear to be randomly distributed and not clustered. As depicted by the bar chart in FIGURE 6b, bright field illumination found 2,279 defects compared to 289 defects found by CF technology. Most interestingly, only 32 of the defects found by CF technology were also found with bright field inspection. 257 defects would have been missed by bright field inspection. The bar chart (FIGURE 6c) shows the size distribution of defects discovered by both techniques. Bright field inspection found a very large number of small defects (less than 5μm) and more defects larger than 25μm. Defects found by the CF technology were between 5-25μm in size.

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FIGURE 7 compares CF technology results (top) and bright field results (bottom). Each vertical pair shows a defect missed by bright field inspection and detected by CF technology. The enhanced brightness and circular shape of the defects detected by the new method strongly imply that they are associated with polymer residues. The enhanced brightness of the defects against the very black background is a unique and valuable feature of CF technology. Overall, these results demonstrate the value of supplementing bright field inspection with CF technology. All of the defects found by CF technology were of sufficient size to impact yield.

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Conclusion

Results shown here demonstrate the benefits of imaging with the new CF illumination technology when compared to conventional bright field illumination. The new technology allows detection of transparent organic residues that are not visible with bright field illumination.

It was also shown to detect types and sizes of defects that were not detected by bright field inspection. Equally important, its ability to reduce noise caused by metal texture and graininess significantly improves its sensitivity to small defects on metal features and dramatically reduces the detection of nuisance defects.

References

1. Gurvinder Singh, et al, “Advanced packaging lithography and inspection solution for next generation FOWLP-FOPLP processing”, IEEE Xplore, October 2016.
2. Woo Young Han, et al, “Inspection challenges in wafer level packaging”, International Wafer Level Packaging Conference, October 2017
3. Jonathan Cohen, et al, “Photoresist residue detection in advanced packaging”, International Wafer Level Packaging Conference, October 2017

Quantenna Communications, Inc. (Nasdaq:QTNA), a developer of high performance Wi-Fi solutions, today announced that Dr. Nambi Seshadri, Quantenna’s chief technologist has been selected as the 2018 IEEE Alexander Graham Bell Medal recipient for exceptional contributions to wireless, networking and engineering. In addition to this highest honor, Seshadri’s prize consists of a gold medal, a bronze replica, a certificate, and an honorarium.

“The innovations by Nambi form the basis for some of today’s Wi-Fi and other wireless networking standards and systems, now in use by billions of Wi-Fi users,” said Dr. Sam Heidari, Chairman and Chief Executive Officer, Quantenna. “We are honored to have such a distinguished and accomplished chief technologist on our team. The process is extraordinarily competitive, this is a great lifetime accomplishment and one of the most prestigious honors that one may receive in our field.”

Every year, the IEEE board of directors selects a SINGLE individual to receive the IEEE Alexander Graham Bell Medal. The selection criteria used include weighing the value of the individual’s contribution to communication among people as well as to communication sciences and engineering, and an evaluation of the contributor, nominator and references. The timeliness of the recognition, and quality of the nomination also are considered.

The IEEE Alexander Graham Bell Medal was established in 1976 by the IEEE Board of Directors, in commemoration of the centennial of the telephone’s invention, to provide recognition for outstanding contributions to telecommunications. The invention of the telephone by Alexander Graham Bell in 1876 was a major event in electrotechnology. It was instrumental in stimulating the broad telecommunications industry that has dramatically improved life throughout the world. As an individual, Bell himself exemplified the contributions that scientists and engineers have made to the betterment of mankind.

In addition to serving as chief technologist to Quantenna, Seshadri is a Professor of Electrical and Computer Engineering (ECE) for the University of California, San Diego. Prior to Quantenna, Seshadri held multiple senior positions at Broadcom Corporation where he helped Broadcom’s wireless initiatives, including it’s foray into cellular, mobile multimedia, low power wireless connectivity, GPS and others. During 2011-2014, he also served as the General Manager of the Mobile Platforms Business Unit. Prior to joining Broadcom Corporation, he was a Member of Technical Staff at with AT&T Bell Lab Laboratories and Head of Communications Research at AT&T Shannon Labs where he contributed to fundamental advances in wireless communication theory and practice.

Seshadri was elected Fellow of the Institute of Electrical and Electronic Engineers (IEEE) in 2000 and was elected to the National Academy of Engineering (USA) in 2012 and as a Foreign Member of the Indian National Academy of Engineering in the year 2013. He holds approximately 200 patents. He was a co-recipient of the IEEE Information Theory Paper Award in 1999 for his paper with Tarokh and Calderbank on space-time codes, and his IEEE Journal on Selected Areas In Communications (JSAC) paper on space-time coding modems with Naguib, Tarokh, and Calderbank was selected by IEEE Communication Society for publication in, “The Best of the Best: Fifty Years of Communications and Networking Research,” for 2003.

A research group in Japan announced that it has quantified for the first time the impacts of three electron-scattering mechanisms for determining the resistance of silicon carbide (SiC) power semiconductor devices in power semiconductor modules. The university-industry team consisting of researchers from the University of Tokyo and Mitsubishi Electric Corporation has found that resistance under the SiC interface can be reduced by two-thirds by suppressing electron scattering by the charges, a discovery that is expected to help reduce energy consumption in electric power equipment by lowering the resistance of SiC power semiconductors.

Electron scattering under the silicon carbide (SiC) interface is limited by three factors: roughness of the SiC interface, charges under the SiC interface and atomic vibration. Credit: 2017 Mitsubishi Electric Corporation.

Electron scattering under the silicon carbide (SiC) interface is limited by three factors: roughness of the SiC interface, charges under the SiC interface and atomic vibration. Credit: 2017 Mitsubishi Electric Corporation.

Electric power equipment used in home electronics, industrial machinery, trains and other apparatuses requires a combination of maximized efficiency and minimized size. Mitsubishi Electric, a leading Japanese electronics and electrical equipment manufacturer, is accelerating use of SiC devices for power semiconductor modules, which are key components in electric power equipment. SiC power devices offer lower resistance than conventional silicon power devices, so to further lower their resistance it is important to understand correctly the characteristics of the resistance under the SiC interface.

“Until now, however, it had been difficult to measure separately resistance-limiting factors that determine electron scattering,” says Satoshi Yamakawa, senior manager of the SiC Device Development Center at Mitsubishi Electric’s Advanced Technology R&D Center.

Electron scattering focusing on atomic vibration was measured using technology from the University of Tokyo. The impact that charges and atomic vibration have on electron scattering under the SiC interface was revealed to be dominant in Mitsubishi Electric’s analyses of fabricated devices. Although it has been recognized that electron scattering under the SiC interface is limited by three factors, namely, the roughness of the SiC interface, the charges under the SiC interface and the atomic vibration, the contribution of each factor had been unclear. A planar-type SiC metal-oxide-semiconductor field-effect transistor (SiC-MOSFET), in which electrons conduct away from the SiC interface to around several nanometers, was fabricated to confirm the impact of the charges.

“We were able to confirm at an unprecedented level that the roughness of the SiC interface has little effect while charges under the SiC interface and atomic vibration are dominant factors,” says Koji Kita, an associate professor at the University of Tokyo’s Graduate School of Engineering and one of scientists leading the research.

Using an earlier planar-type SiC-MOSFET device for comparison, resistance was reduced by two-thirds owing to suppression of electron scattering, which was achieved by making the electrons conduct away from the charges under the SiC interface. The previous planar-type device has the same interface structure as that of the SiC-MOSFET fabricated by the electronics maker.

For the test, Mitsubishi Electric handled the design, fabrication and analysis of the resistance-limiting factors and the University of Tokyo handled the measurement of electron-scattering factors.

“Going forward, we will continue refining the design and specifications of our SiC MOSFET to further lower the resistance of SiC power devices,” says Mitsubishi Electric’s Yamakawa.

This research achievement was announced at the 63rd International Electron Devices Meeting (IEDM) in San Francisco, California, on December 4, 2017.

SEMI, the global industry association representing the electronics manufacturing supply chain, today reported that worldwide semiconductor manufacturing equipment billings reached US$14.3 billion for the third quarter of 2017.

Quarterly billings of US$14.3 billion set an all-time record for quarterly billings, exceeding the record level set in the second quarter of this year. Billings for the most recent quarter are 2 percent higher than the second quarter of 2017 and 30 percent higher than the same quarter a year ago. Sequential regional growth was mixed for the most recent quarter with the strongest growth in Europe. Korea maintained the largest market for semiconductor equipment for the year, followed by Taiwan and China. The data are gathered jointly with the Semiconductor Equipment Association of Japan (SEAJ) from over 95 global equipment companies that provide data on a monthly basis.

Quarterly Billings Data by Region in Billions of U.S. Dollars
Quarter-Over-Quarter Growth and Year-Over-Year Rates by Region
3Q2017
2Q2017
3Q2016
3Q2017/2Q2017
3Q2017/3Q2016
Korea
4.99
4.79
2.09
4%
139%
Taiwan
2.37
2.76
3.46
-14%
-32%
China
1.93
2.51
1.43
-23%
35%
Japan
1.73
1.55
1.29
11%
34%
North America
1.50
1.23
1.05
22%
43%
Europe
1.06
0.66
0.53
61%
100%
Rest of World
0.74
0.62
1.13
20%
-34%
Total
14.33
14.11
10.98
2%
30%

Source: SEMI (www.semi.org) and SEAJ (http://www.seaj.or.jp)

The Equipment Market Data Subscription (EMDS) from SEMI provides comprehensive market data for the global semiconductor equipment market. A subscription includes three reports: the monthly SEMI Billings Report, which offers a perspective of the trends in the equipment market; the monthly Worldwide Semiconductor Equipment Market Statistics (WWSEMS), a detailed report of semiconductor equipment billings for seven regions and 24 market segments; and the SEMI Semiconductor Equipment Forecast, which provides an outlook for the semiconductor equipment market. More information is also available online: www.semi.org/en/MarketInfo/EquipmentMarket.

On October 27, SEMI China held a kickoff meeting for a new FlexTech Committee in Suzhou. FlexTech, a SEMI Strategic Association Partner, is devoted to fostering the growth, profitability and success of the flexible and printed electronics supply chain, and enabling the many smart products enabled by this new class of electronic intelligence. FlexTech offers collaboration opportunities among industry, academia, and research organizations working in the field.

Flexible, hybrid and printed electronics (FHE) are being designed into a wide range of products on the market today, in both consumer and industrial segments. These products include, components in today’s cell phones, human and health performance tools, security tags, sensor componentry in cars and airplanes, agricultural and environmental sensors, strain gauges in bridges and equipment, just to name a few.  Flexible electronic technology also intersects semiconductors, packaging, testing, materials, chemical, printed circuit boards, and display industries – for a total market size of one trillion yuan, and boosting the transformation of traditional industries in China.

China-FlexTech-photo1

Through group discussion at the meeting, Cui Zheng, researcher of SINANO of the Chinese Academy of Sciences, was elected Chairman of the committee. Zhang Jie, vice president of Changzhou Institute of Printed Electronics Industry, was elected Vice Chairman of the committee. SEMI FlexTech CTO Dr. Melissa Grupen-Shemansky gave the letter of appointment to the two appointees. Committee members hail from many different companies in the flexible, hybrid and printed electronics industry, including:

  • Applied Materials: Technology Director Sun Zhenghong
  • Beijing Institute of Graphic Communication: Professor Wang Wei
  • Beijing Sineva Technology Co., Ltd.: General Manager Zhang Mi
  • Guangdong Juhua Printing Display Technology Co., Ltd.: General Manager Fu Dong
  • Guangzhou OED Technologies Co., Ltd.: General Manager Wang Xidu
  • Guangzhou New Vision Opto-Electronic Technology Co., Ltd.: General Manager Wang Lei
  • Guangdong University of Technology:  Professor Cui Chengqiang
  • Royole Corporation: Marketing Department Director Dang Pangfeng
  • Semiconductor Institute of Chinese Academy of Sciences: Researcher Shen Guozhen
  • Shanghai Jiao Tong University: Professor Guo Xiaojun
  • Shenzhen Laibao Hi-Tech Co., Ltd.: Vice General Manager Wang Shimin
  • Sun Yat-Sen University: Professor Yang Boru

During the meeting, SEMI FlexTech CTO Dr. Melissa Grupen-Shemansky introduced FlexTech and its efforts in fostering an FHE eco-chain, including market research, R&D, and final pilot manufacturing. She expressed her optimism for strong FHE opportunities in China.

In the second half of the meeting, GM Wang Lei of Guangzhou New Vision Opto-Electronic Technology Co., Ltd. gave an introduction on the development trends of flexible OLED displays, researcher Shen Guozhen of the Semiconductor Institute of Chinese Academy of Sciences shared the research on soft sensor and multi-functional system based on low-dimensional semiconductor nanostructures, and Guangdong University of Technology Professor Cui Chengqiang presented applications for flexible packaging substrates in chip packaging.

The participants were also invited to visit the SINANO of the Chinese Academy of Sciences, where Dr. Zhang Dongyu gave a detailed introduction to the latest results of the research center.

The SEMI China FlexTech Committee will serve as an important tie between China and the global flexible hybrid and printed electronics industry.

For more information on SEMI China, visit http://www.semichina.org/index.html .

See-through electronic devices, such as transparent displays, smart windows and concealed circuits require completely translucent components if users are to digitally interact with their perceived surroundings and manipulate this information in real time. Now, KAUST researchers have devised a strategy that helps to integrate transparent conducting metal-oxide contacts with two-dimensional (2D) semiconductors into these devices.

Ultrathin semiconductor sheets that are composed of transition metals associated with chalcogen atoms, such as sulfur, selenium and tellurium, present exceptional electronic properties and optical transparency. However, to date, incorporating molybdenum sulphide (MoS2) monolayers into circuits has relied on silicon substrates and metal electrodes, such as gold and aluminum. The opacity of these materials has stalled attempts to develop fully transparent 2D electronic devices.

The KAUST team led by material scientists Xi-Xiang Zhang and Husam Alshareef has combined MoS2 monolayers with transparent contacts to generate a series of devices and circuits, such as transistors, inverters, rectifiers and sensors. The contacts consisted of aluminum-doped zinc oxide (AZO), a low-cost transparent and electrically conductive material that may soon replace the widely used indium-tin oxide. “We wanted to capitalize on the excellent electronic properties of 2D materials, while retaining full transparency in the circuits,” explains Alshareef.

According to Alshareef, the researchers grew the contacts over a large area by atomic-layer deposition, during which individual atom layers precisely accumulate on a substrate. Their main difficulty was to also form high-quality MoS2 monolayers on silicon-based substrates over a large area. “We overcame this by using an interfacial layer that promotes MoS2 growth,” says Alshareef.

The team also developed a water-based transfer process that moves the as-deposited large-area monolayers onto a different substrate, such as glass or plastic. The researchers then deposited the AZO contacts on the transferred 2D sheets before manufacturing the devices and circuits.

The resulting devices outperformed their equivalents equipped with opaque metal contacts, such as gate, source and drain electrodes, which demonstrates the high compatibility between transparent conducting metal-oxide contacts and MoS2 monolayers. “The transistors fabricated by the large-area process showed the lowest turn-on voltage of any reported MoS2 monolayer-based thin-film transistor grown by chemical vapor deposition,” says PhD student Zhenwei Wang, first author of the study.

“Additional circuits are planned that will help demonstrate that our approach is robust and scalable” says Alshareef.

By Walt Custer, Custer Consulting

SEMICON Europa 2017 and productronica were co-located November 14 to 17 at Messe Munchen in Munich, Germany. Attendance was very good and the mood was upbeat.

The third quarter of this year has seen broad growth both globally and also for the European electronic supply chain.

Chart 1 shows 3Q’17/3Q’16 growth by electronic sector for the world. SEMI and PCB process equipment and semiconductors stand out but almost all key sectors expanded.

Custer-Chart-1-Global-Elec-

Chart 2 shows third quarter growth for Europe.  SEMI equipment leads but the third quarter Eurozone expansion was broad based.

Custer-Chart-2-EUropean-Ele

At productronica, Custer Consulting presented at the “Business Outlook for the Global Electronic Supply Chain” event (with emphasis on Europe).  For a copy of Walt’s charts, please email [email protected].

GLOBALFOUNDRIES and Ayar Labs, a startup bringing optical input/output (I/O) to silicon chips, today announced a strategic collaboration to co-develop and commercialize differentiated silicon photonic technology solutions. The companies will develop and manufacture Ayar’s novel CMOS optical I/O technology, using GF’s 45nm CMOS fabrication process, to deliver an alternative to copper I/O that offers up to 10x higher bandwidth and up to 5x lower power. This cost-effective solution is integrated in-package with customer ASICs as a multi-chip module, and improves data speed and energy efficiency in cloud servers, datacenters and supercomputers. As part of the agreement, GF has also invested an undisclosed amount in Ayar Labs.

Modern data centers and cloud applications require high-performance, power-hungry chips to process and analyze huge volumes of data in real time. Growth in chip I/O capabilities has not matched exponential increases in computing power, because of physical limitations in electrical data transmission. Optical I/O, which leverages optical components on the CMOS die to transmit data at rapid speeds, will be a key enabler to overcoming the limitations of today’s data center interconnects. In addition, Ayar’s technology reduces power consumption at both the network and processor level.

“GF has demonstrated true technology leadership in recognizing optical I/O as the inevitable next step as we move into a More than Moore world,” said Alex Wright-Gladstein, CEO at Ayar Labs. “This collaboration between Ayar and GF could improve chip communication bandwidth by more than an order of magnitude and at lower power, and is a validation of Ayar’s viability in the current semiconductor ecosystem. This collaboration will unlock a larger market opportunity, expanding both our and GF’s customer base. We look forward to working with GF to help solve the interconnect problems of today’s chips and create greater value for our customers than if both companies worked independently.”

“The Ayar Labs team has been designing cutting-edge silicon photonics components on GF’s technology for the past eight years and has achieved exceptional results,” said Mike Cadigan, senior vice president of global sales and business development at GF. “Our strategic collaboration builds on our relationship, leveraging GF’s silicon photonics IP portfolio and our world-class manufacturing expertise to enable faster and more energy-efficient computing systems for data centers.”

The collaboration brings together Ayar Labs’ patented IP in optical technology with GF’s best-in-class expertise in silicon photonics to co-develop optical solutions that will be fabricated using GF’s process technology. The availability of this technology, including certain Design IP cores, will enable internet service providers, system vendors and communication systems to push data capacity to 10 Tera bits per second (Tbps) and beyond, while maintaining the low energy and cost of optical-based interconnects.

Electronics manufacturing executives will attend Europe’s SEMI Industry Strategy Symposium (ISS Europe) in Dublin, Ireland on 4-6 March. Hosted by SEMI Europe, the ISS Europe 2018 is the three-day flagship business event that brings together leading analysts, researchers, economists, and technologists for critical insights on the forces shaping the electronics manufacturing supply chain.

While having core strengths of its own, Europe is part of a global innovation and supply chain and European organisations need to find new ways to maximise competitive advantage. “Organisations operating in Europe need to find the most effective way to innovate, manufacture and profit by finding their place in the global supply chain. During the symposium, best class discussions will address Europe’s strategic, economic and social needs“ said Laith Altimime, president, SEMI Europe.

A wide range of top European companies, research institutes and public institutions will debate the best ways to compete globally, along with discussions on successful manufacturing in Europe and mechanisms to support innovation:

Speaker Line-up:

  • David Bloss, VP, Technology Manufacturing Group, Intel
  • Holger Blume, Professor, University of Hanover
  • Jean-Frederic Clerc, Deputy CEO and CTO, CEA Tech
  • Kevin Cooney, Senior VP and Managing Director, Global CIO, Xilinx EMEA
  • Jean-Christophe Eloy, CEO, Yole Développement
  • Ann-Charlotte Johannesson, CEO, CEI-Europe AB
  • Cheryl Miller, Founder/Executive Director, Digital Leadership Institute
  • Mick A Morris, Director AMBER Research Centre, Professor, Trinity College Dublin
  • Alain Mutricy, Senior VP Product Management, GLOBALFOUNDRIES
  • James O’Riordan, CTO, S3
  • David Sneddo, Director of Large Customer Sales for Central Europe, Google
  • Florien van der Windt, Cluster Manager Smart Mobility, Dutch Ministry of Infrastructure & Environment
  • Hanns Windele, Vice President, Europe and India, Mentor, a Siemens Business

Highlight of this year, the Panel Discussion “Critical Strategies to Grow Europe in the Global Supply Chain”. SEMI will also offer great networking opportunities such as an opening networking reception and, a gala dinner during which SEMI will announce the 2017 European Award winner.

Join Europe’s strategic thinkers and business drivers at ISS Europe 2018 in Dublin, Ireland from March 4-6, 2018!

For further information about our programs, please visit www.semi.org/eu/iss-europe-2018 or contact Christina Fritsch, Senior Manager, Program and Events. To sponsor the event please contact: SEMI Europe, Denada Hodaj, Manager Sales Europe (email: [email protected]). Register before January 31 for a discount. Fee includes conference and presentations access, reception, lunches and dinner. To register online, please visit: https://iss2018.besl-eventservice.de/front/index.php

 

Global demand for flat panel displays by area is forecast to grow 7.2 percent to 210 million square meters in 2018 compared to 2017, according to IHS Markit (Nasdaq: INFO). That will be the biggest annual growth since 2014.

“Growth in demand for flat panel displays next year will be mainly driven by migration to large displays, declining panel prices, and high expectations for a recovery in the global economy,” said Ricky Park, director at IHS Markit.

171120_Flat_Panel_Demand

The rise in demand area is largely attributed to a fall in retail prices of applications along with a drop in panel prices, which is expected to spur consumers’ appetite for various display devices. The sharp fall in panel prices in the second half of 2017 should soon be reflected in the prices of consumer electronics goods in the upcoming peak shopping seasons later this year and in early 2018. The cheaper panel prices are also expected to bolster demand for larger display products. As Gen 10.5 fabs are due to start operation in the first half of 2018, supply of super large TV panels, including 65- and 75-inch products, is projected to grow, according to the Display Long-term Demand Forecast Trackerreport by IHS Markit.

Increasing adoption of bezel-less flexible organic light-emitting diode (OLED) display in smartphones will lead to a growth in the size of overall smartphone displays next year. “Launches of new smartphones with large screens should stimulate consumers’ demand to replace their old phones,” Park said.

The flat panel TV market is also expected to see a significant rise in replacement demand, following the transition into digital broadcasting from analogue signal that started in late 2000s. TV sales in markets where the digital transition was completed in late 2000s grew at 10 to 21 percent in 2009 and 2010, much faster than the compound annual growth rate of 3 percent between 2004 and 2014. “A consumer’s TV replacement cycle is usually about 10 years,” Park said. “A hike in replacement demand for the next few years is expected.”

The global flat panel market will also get a boost from higher demand for new and larger TVs ahead of the 2018 PyeongChang Winter Olympics scheduled in February and the 2018 FIFA World Cup in Russia in June. “Panel sales in even years when major world sports events were held had grown at a faster rate than in odd years,” Park said.

In addition, the ongoing recovery in the global economy bodes well for the panel demand. Global gross domestic product (GDP) is forecast to grow 3.2 percent in 2018, following 3.1 percent in 2017 and 2.5 percent in 2016, according to IHS Markit. In particular, the economic recovery in North America and emerging markets, such as India, Brazil and Russia, is expected to be stronger than the previous year. A rise in non-ferrous metal prices, often a precursor to an economic recovery, is another positive sign.

Unlike the strong gain in demand by area, the growth in the global flat panel market in value is, however, projected to be restrained by the fall in the panel price in the second half of 2017. The panel demand by value is forecast to rise 1 percent to $126 billion in 2018 from 2017, according to IHS Markit.