Scalable SONOS based embedded non-volatile memory technology


SONOS (Si-Oxide-Nitride-Oxide-Si) based eNVM technology is well-suited for System-On-a Chip (SOC) products as they are very compatible with standard logic/mixed-signal CMOS process flow. This paper describes how the SONOS based eNVM technology has been successfully developed and scaled down to 28nm node. With the shrink, SONOS has been seamlessly integrated into advanced front-end process flows with novel features such as stress enhancement techniques and High K-Metal Gate. Process/integration innovations have enabled the design rule shrink by minimizing the Vt variations of the memory cell devices in-spite of enhanced impact of dopant fluctuations. In addition, optimizations of the SONOS gate stack also have enabled the memory to have very high reliability even with scaling.


Critical factors for the choice of the NVM technology for an embedded memory include the cost of integration and the extent of its impact on the baseline CMOS device performance. SONOS is superior in both respects due to the simplicity of its integration (fewer extra lithography masks) as shown in FIGURE 1 and the minimal impact on CMOS device performance (FIGURE 2) which means baseline device models are not affected by the integration. This gives a significant edge to SONOS for multiple product applications.

FIGURE 1. Typical process flow for SONOS integration.

FIGURE 2. Device performance matching.


A SONOS device structure and 2T-SONOS cell are schematically shown in FIGURE 3.

The cell consists of a SONOS Control Gate (CG) in series with a CMOS Select Gate. Structurally both are MOSFETs with the CG having a ONO gate dielectric and SG having a SiO2 or High K based gate dielectric. The CG is the memory device in which charge injected from the Si substrate across the thin tunnel oxide by Fowler-Nordheim tunneling is trapped in the Nitride (N) layer of the ONO stack. The charge can be either Positive (hole trapping) or negative (electron trapping) depending on the polarity of voltage applied to the gate. The trapped charge changes the threshold voltage (Vt) of the CG between a “Program (VTP)” and an “Erase (VTE)” state. The difference in Vt between the program and erase staes defines the memory window.

SONOS memory cell performance

The program/erase efficiency of a SONOS memory cell determines how well it can be programed or erased. The Vts and Vt window are determined by the voltage appled across the ONO dielectric of the CG and the time duration of the program/erase pulse. The reliability of the memory cell defines its ability to maintain window enough to sense the two states clearly during the entire life of the memory. The initial window is maximized by optimizing the SONOS stack and program/erase conditions using the progamming  curves which show how the VTP and VTE vary wit program/erase pulse width (FIGURE 4a).

FIGURE 4. Program-Erase characteristics of SONOS cell with (a) Normal and (b) thicker top oxide.

The saturation in the VTE clearly indicates that the charge in the nitride, during erase, stops increasing because the additional hole charge injected from the substrate is compensated by the electron charge injected from the gate to the nitride. The injection from the gate is determined by the thickness and quality of the top oxide. Thinner or poor quality top oxide leads to increased injection from gate and shows increased erase saturation while a physically thicker top oxide drastically reduces injection from gate and hence results in much lower erase saturation (FIGURE 4b).

Endurance and Data Retention are the most critical specifications for a NVM and these reliability requirements are becoming more stringent as embedded NVM products are getting into new markets such as automotive electronics. SONOS typically has good endurance performance (FIGURE 5a). With the engineering of a unique, proprietary ONO stack, robust retention performance has been achieved for all Cypress products (FIGURE 5b). On certain integration flows, SONOS eNVM can meet automotive retention specs.

FIGURE 5. SONOS Reliability – (a) Endurance (b) Retention.

SONOS cell scaling – Vt uniformity

To meet the ever increasing demand for larger memories, the SONOS memory cell is shrunk by moving to more advanced technologies to take advantage of tighter design rules. Cell size trend with technology nodes, demonstrated on Silicon, is shown in FIGURE 6 for two types of SONOS cells, Dedicated Source Line (DSL) and Common Source Line (CSL).

FIGURE 6. Trend of SONOS cell size.

The key challenege for the shrink is the degradation of Vt uniformity on account of increased impact of Random Dopant Fluctuations (RDF) at the surface of the channel of the SONOS device. This can be due to the inherent effect of dopants enhanced by diffusion of dopants during high temperature steps. For successful shrink, several process modifications, especially reduction of dopants in the surface of the channel of CG and use of deeper channel implants with heavier species such as Indium is required so as to keep surface dopant concentrations low. In addition, doping by species such as Carbon can reduce the transient enhanced diffusion of channel dopants. Reduction in thermal budget after SONOS stack formation also lowers the diffusion of dopants to the surface and hence reduces RDF. With the use of such techniques, the Vt sigma can be kept reasonably low with technology shrink as shown in FIGURE 7.

FIGURE 7. Vt sigma trend with technology shrink.

The impact of new doping strategies on maintaining a low Vt sigma is clearly seen in this trend which shows how process optimizations lowers sigma in all technology nodes. At the beginning of technology development such as in 28nm node, the sigma is typically high. With process and /or cell optimizations, the sigma becomes lower. A typical example of Vt sigma improvement with reduction in the diffusion of dopants to the surface of channel of CG is shown in FIGURE 8 below.

FIGURE 8. Vt sigma improvement.

Maintaining a low sigma greatly helps to minimize the flash yield loss due to widening of Vt distribution at Beginning of Life (BOL) and at End of Life (EOL), typically after a high temperature bake.

SONOS integration into High K-Metal gate process flow

With the transition of CMOS technology to High K-Metal Gate (HKMG) at 28nm node and beyond, it is imperative that SONOS be compatible with HKMG. This has been demonstrated at 28nm node with an integration approach that has the HK dielectric as part of the top oxide of the ONO stack and the MG as the gate of the CG. This is a true integration of HKMG into SONOS device and enables embedded memory products in very advanced technology nodes. Endurance and retention curves for a SONOS cell with HKMG (FIGURE 9) show that robust reliability can be achieved with a greatly shrunk NVM cell.

FIGURE 9. Endurance and Retention of SONOS cell integrated into High K-Metal Gate process flow.

Figure 9b.

SONOS for analog NVM

Analog memory is emerging as a strong candidate for “AI edge” applications. Analog NVM uses NVM array with all WLs turned on in 1 block to sum currents. Power needed for making an “inference” is ~1000X lower using analog NVM compared to GPU. Applications are in speech processing, image processing etc. without uploading to the cloud. The memory has multiple levels (8 or 16) and each ID/VT level is a “weight” for the inference and 16 levels can give very low error rates.  ~1-3% overlap of distributions between neighboring VT levels is acceptable.

Key requirements for analog memory for AI edge are

  1. 8 to 16 ID/VT levels between 1E-11A to 1E-5A (lower current levels improve power efficiency)
  2. To achieve ~1-3% overlap of distributions we need levels to be ~5sigmas apart (peak to peak)
  3. Uniform subthreshold slope is preferred, otherwise there is larger error in targeting different ID levels
  4. 1K cycles endurance is sufficient; cycle-to-cycle stability in ID is required (no issue for SONOS)
  5. Refresh of weights possible once a year (1 year at 55C retention is acceptable)
  6. Program time of whole array is a concern

SONOS is a very promising option for the analog memory with multiple levels due to the low Vt sigma. This can be achieved by programming / erasing the SONOS cell to different but distinct Vt or Cell current values, separated by gaps required to sense them as different states of the memory. Soft program or erase is used to place the memory cell at distinct target Vt/Id values with a tight distribution. An illustration of this concept, achieved on test structure arrays is shown in FIGURE 10.

FIGURE 10. Multiple Vt (left) or Id (right) levels of analog SONOS memory.

Although this data is preliminary, it shows that SONOS array can be used for analog memory with the right conditions of program/erase.


It is clear from the above sections that SONOS is a very strong option for eNVM in all advanced nodes, the key advantage being the simplicity of integration into a baseline flow. In addition, it seems to be a very good option for analog memory used in AI edge applications.



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