02/02/2011 

All the major semiconductor players are embracing 3D integration, says Simon Deleonibus. The CEA-Leti scientist and IEEE Fellow wants to see TSV mature and new technologies develop based on wafer bonding. He speaks with Debra Vogler.

01/21/2011 

CEA-Leti signed a multiyear agreement with SHINKO ELECTRIC INDUSTRIES CO. LTD. to develop advanced semiconductor packaging technology. They will focus on volume production of silicon interposers.

01/19/2011 

Dr. Phil Garrou looks ahead to a laundry list of changes coming in the next ITRS Update with respect to assembly and advanced packaging, including 3D integration, interposers, and applications from medical to automotive and embedded applications.

01/17/2011 

CEA-Leti is expanding its technology offering, ramping up one of Europe’s first 300mm lines dedicated to 3D-integration applications. The new line is dedicated to R&D and prototyping and includes 3D-oriented lithography, deep etching, dielectric deposition, metallization, wet etching, and packaging tools.

01/12/2011 

The 2010 Update to the International Technology Roadmap for Semiconductors (ITRS), while not one of the scheduled major revisions, nevertheless includes substantial changes have occurred in 2010, including boosts in the timelines for NAND flash and DRAM device rollouts, backup plans for lithography forced by EUV delay, impending device and interconnect structural changes, and progress in 3D packaging.

01/11/2011 

Paul Kirby, FEI, provides insights on the shift to complex 3D device structures and complex interconnect methods such as TSV. In the future, 3D analysis techniques could play increasingly important roles, he says. In advanced packaging, failure analysis is more critical because multi-die stacks can fail due to one bad die. This is an online exclusive essay in SST's Forecast for 2011: Back to Reality series.

01/11/2011 

Arthur W. Zafiropoulo, Ultratech, sees the 20/22nm node as a competition for gate-first and gate-last proponents to discover which will lead the semiconductor industry. Device makers that master TSV chip stacking will be the winners over the course of this decade, he says. This is an online exclusive essay in SST's Forecast for 2011: Back to Reality series.

01/07/2011 

Dr. Phil Garrou takes a closer look at an IP dispute lobbed by Ziptronix against Omnivision and TSMC over low-temperature oxide bonding, used in making backside-illumination CMOS image sensors.

01/06/2011 

Fresh off 3D announcements of IBM and Samsung, several industry leaders talked about the imminent use of 3D Interposers at the RTI 3-D Architectures for Semiconductor Integration and Packaging Conference in Burlingame CA, reports Dr. Phil Garrou.

01/03/2011 

Laurent Clavelier, head of solar technologies department at Leti, discusses the significance of Leti's IEDM paper #2.6 "Engineered substrates and 3D integration technology based on direct bonding for future More Moore and More than Moore integrated devices" with Debra Vogler, senior technical editor.

12/22/2010 

3D IC technology will require significant changes across the design, tool, and manufacturing spectrum -- that sounds a lot like how the industry transitioned from bipolar to CMOS, writes Dr. Phil Garrou, reporting from themes at an IEEE 3D event in Munich.

12/15/2010 

Dr. Phil Garrou looks at 3D IC technology discussions at IEDM 2010, including details of TSMC's integration of 3D into its advanced CMOS foundry processes, and a close examination of 3D-induced stresses.

12/15/2010 

Techcet's Michael A. Fury reports in-depth from sessions at IEDM 2010, looking at papers on NAND flash using airgaps, a lock-and-key method for 3D integration, RF performance of graphene FETs, and FET-built DNA biosensors.

12/14/2010 

SEMATECH, the SIA, and SRC have established a new 3D Enablement program targeting standards in inspection, metrology, microbumping, bonding, and thin wafer and die handling.

12/11/2010 

AT&S debuted a new technology to enable system-in-package (SiP) devices. AT&S’s embedded component packaging technology ECP is used to enable further miniaturiztion of electronic devices while enhancing their performance.

12/08/2010 

Innovative Micro Technology Inc. (IMT) added a new geometry point in its technology roadmap for through silicon vias (TSVs). Joining the copper-filled 15 by 60um depth TSV configuration that has been in production for nearly 2 years, 50 by 250um copper-filled TSV is planned for production at the beginning of 2011.

12/07/2010 

SEMI International is forming a standards committee to evaluate and create specifications and practices for 3D stacked ICs (3DS-IC), with initial efforts targeting three areas: bonded wafers, inspection/metrology, and thin wafer handling.

12/06/2010 

Dr. Nagesh Vodrahalli, vice president of technology and manufacturing at ALLVIA, will present a discussion on December 9 titled "Silicon Interposers with TSVs and Embedded Capacitors for Advanced Logic Applications."

12/01/2010 

Tegal Corporation (Nasdaq: TGAL) is launching a new member of its ProNova family of high-density inductively coupled plasma (ICP) reactors for the company’s DRIE series wafer processing products. The ProNova2 is targeted for fast-growing 200mm MEMS and 3D IC applications.

12/01/2010 

The test community is embracing 3D ICs, as evidenced by presentations at the first IEEE International Workshop on Testing 3D stacked ICs that addressed a range of test challenges and solutions, reports Dr. Phil Garrou.