05/30/2006 May 30, 2006 - X-Fab Semiconductor Foundries has ported its 0.6-micron CMOS technology with trench isolation to new silicon-on-insulator (SOI) substrates, offering up to 40% smaller die size and cost-competitiveness with CMOS technology.
05/30/2006 May 30, 2006 - AMD plans to spend an additional $2.5 billion over the next three years to boost output at its semiconductor production facilities in Dresden, Germany, by converting some 200mm capacity to 300mm and building a new cleanroom.
05/30/2006 May 30, 2006 - Suss MicroTec and IBM say they have completed initial reliability testing for 300mm lead-free C4NP solder-bumped wafers, and are building a final toolset for high-volume production.
05/30/2006 Reaction is mixed to a petition filed by consumer, health and environmental groups that asked the Food and Drug Administration to recall sunscreens that contain nanoparticles unless they are proven safe.
05/26/2006 May 26, 2006 - FlipChip International LLC and Engent Inc. are partnering to develop 3D wafer-level CSP (WLCSP) technologies, seen as a low-cost alternative to system-on-chip for highly integrated stacked die packaging applications.
05/26/2006 May 26, 2006 - Nantero Inc., Phoenix, AZ, and ON Semiconductor will pick up where Nantero and LSI Logic left off with work to integrate carbon nanotubes into CMOS fabrication. ON Semi acquired LSI Logic's facility in Gresham, OR, earlier this year, where the technology was being developed.
05/26/2006 May 26, 2006 - South Korea's Dongbu Electronics and Cadence Design Systems Inc. have developed an RTL-to-GDSII reference flow for 0.13-micron semiconductor manufacturing process technologies.
05/26/2006 May 26, 2006 - Analysis from two firms predicts a soft market for lithography equipment in 2008, after leading-edge chipmakers are through placing initial orders for next-generation lithography tools.
05/26/2006 May 26, 2006 - Attendees at the SEMATECH-sponsored Litho Forum in Vancouver, BC, May 22-24 discussed the readiness of lithography technologies for the 32nm half-pitch and beyond technology generations, seen beginning in 2012, following the 45nm node generation expected to begin production in 2009.
05/26/2006 Phoenix, AZ — Aiming to speed up development and deployment of 3-D wafer-level chip-scale packages(WLCSP) for integrated stack-die packages, FlipChip International (FCI) and Engent have formed a strategic alliance. FCI specializes in wafer-level bumping, while Engent's focus is 3-D flip chip assembly.
05/26/2006 'Magic Nano,' the protective glass and bathroom sealant that was recalled in late March in Germany after causing severe breathing problems for some consumers, did not contain any nanoparticles. That¿s according to Rene Zimmer of the Federal Institute for Risk Assessment (BfR) in Berlin.
05/25/2006 May 25, 2006 - Taiwan's top chip assembly houses are lining up to get government approval to open facilities in mainland China, following the government's decision to limit restrictions on transfers of some technologies
05/25/2006 May 25, 2006 - SEMATECH and the U. of Queensland, Brisbane, Australia, have agreed to codevelop new resists for 193nm immersion lithography, in an effort to extend immersion technology for multiple generations.
05/25/2006 May 25, 2006 - Worldwide IC capacity rose 4% during 1Q06, while output inched up about 2%, and utilization rates slipped below the 90% mark for the first time since last summer, according to new data from Semiconductor International Capacity Statistics (SICAS).
05/25/2006 Munich, Germany — Freescale Semiconductor recently ordered one of SUSS MicroTec's ABC200 automated production wafer-bonding systems. Silicon wafer bonding is a critical wafer-level packaging technology and an enabling technology for the mass production of cost-effective MEMS accelerometers for Freescale, so SUSS' automated production wafer bonders ideally suit their needs.
05/25/2006 In a one-on-one interview at The ConFab, Charles Huang, SVP of SMIC's Shanghai operation, followed up on his Monday presentation about general strategies foundries can take to produce next-generation semiconductor technology, and outlined his company's plans to exploit the burgeoning demand for ICs in China -- now the world's largest regional IC market.
05/25/2006 During a ConFab panel discussion on "Solutions to the R&D Challenge," Simon Yang, senior VP and CTO of Chartered Semiconductor Manufacturing, called for greater support of an industry-wide "open ecosystem of R&D" to deal with the impending R&D crisis. Several factors are converging to create a perfect storm in R&D, he said -- as scaling approaches physical limits, profit margins for technology and manufacturing companies are shrinking, and R&D operation costs are escalating out of control.
