June 25, 2007 – Freescale Semiconductor says it has developed a “multicore communications platform” architecture based on 45nm process technologies and a Power Architecture core, and a scalable on-chip “fabric” for on-chip connectivity of 32 or more cores.

“Rather than throwing a bunch of low-performance CPUs together, Freescale is combining several powerful e500 CPUs in a single device,” said Linley Gwennap, principal analyst of The Linley Group, in a statement. “Using its system-on-a-chip experience, Freescale then adds a high-speed fabric, offload of critical functions and intelligent I/O. This combination will keep the CPUs operating at a high level of efficiency.”

The architecture includes a multilevel, cache-coherent hierarchy, with a L2 cache with each core as well as multi-MB shared L3 cache. It includes an enhanced Power Architecture 3500-mc core (top frequency: 1.5GHz), and a “CoreNet” technology that can accommodate more than 32 cores. A hypervisor environment enables multiple individual operating systems to share system resources, including processor cores, memory, and other on-chip functions.

“This is a comprehensive SoC architecture based on a cache-coherent and extensively scalable approach to multi-core design,” said Lynelle McKay, SVP and GM for Freescale’s networking and computing systems group. “We believe this platform and its ecosystem of enablement will unlock the real potential of multi-core processing, establish new industry benchmarks for total networking performance and dramatically streamline multi-core development.”

First products based on the new multicore platform are slated to sample in late 2008. A simulation environment is now available for Freescale’s current generation of multi-core processors, and compatibility with the multicore platform is expected to be available in 4Q07.