By Phil LoPiccolo, Editor-in-Chief
Among the noteworthy developments to be discussed at this year’s International Interconnect Technology Conference (IITC, June 4-6 in Burlingame, CA) are advances in fabricating carbon nanotubes (CNTs) for use in via applications. Presentations on the topic will include a paper from MIRAI-Selete that describes a novel process for forming CNT vias, and reports CNT interconnect performance characteristics that would meet requirements for the 32nm node and beyond. In related work, a team from Rensselaer Polytechnic Institute (RPI) will present a technique to increase the density of post-growth CNT bundles to improve conductivity, potentially beyond that of copper.
Much attention has been focused recently on replacing copper with CNT bundles for interconnect applications, given CNTs’ excellent electrical properties. They are among the few materials that could exceed the 1×107A/cm2 current density that the ITRS says will be needed at the 32nm generation;they appear to exhibit ballistic conduction, whereby electron scattering from defects or impurities is absent or negligible; and they have the potential to be grown in via holes with high aspect ratios, without the complications of copper deposition.
Last year, Fujitsu reported selective growth of vertical CNT bundles in 40nm via holes uniformly across 300mm wafers at temperatures of ~450°C, moving closer to matching the resistance of copper at CMOS-compatible growth temperatures of 400°C (See SST Tech News, Dec 2006, pg. 22.) Building on that work, a team at MIRAI-Selete in Japan is now reporting it has designed a damascene process for fabricating vertically aligned, multi-walled nanotubes (MWNTs) with 10nm dia. and a density of 3×1011/cm2 in 160nm dia. via holes. Once the via holes are formed over bottom Cu interconnect, and barrier and contact layers are deposited, MWNTs are grown not only in the via holes, but also across the entire substrate surface, using Cobalt catalyst nanoparticle deposition and thermal CVD at 450oC (see images above). After a spin-on glass coating is applied, CMP processing shaves off the excess CNTs, and the top Cu interconnect is formed.
Electrical analysis indicates the lowest resistance of CNT vias to date (0.05-ohms), according to the researchers. In addition, an estimated electron mean free path of about 80nm corresponds to the via height predicted for 32nm node technology in ~2013.
In other CNT work, a team from RPI in Troy, NY, will discuss a method to significantly increase the site density, and thereby further reduce the resistance, of CNT bundles. A technique to grow closely packed CNT bundles has proven elusive, so the RPI group focused instead on densifying bundles that have already been grown. CVD-grown, vertically oriented CNTs are immersed in an organic solvent; when the solvent evaporates, the individual nanotubes reportedly aggregate into higher-density bundles by capillary coalescence and remain together by van der Waals forces (see image below).
According to the team, the technique increases the density of the bundles by a factor of 5x-25x, depending on bundle height, dia., pitch, and specific CNT properties. Using CMP to remove the ends of the densified CNTs creates cylindrical or nail-shaped bundles that can be used as building blocks for CNT interconnects, the researchers explain, adding that CNT bundless are a promising candidate for next-generation IC interconnect largely because they can carry a high current density (~109 A/cm2) and demonstrate ballistic transport. Moreover, they note that CNTs can potentially have higher conductivity than copper if they are closely packed, given that denser CNTs means more conduction channels are available, and thus less resistance is expected. — P.L.