by Debra Vogler

The proliferation of DFM start-ups has set the stage for a plethora of announcements in the months leading up to the SPIE Microlithography Conference. Another entrant trying to alter the DFM landscape is Clear Shape Technologies, backed by several venture capital supporters (including the VC arms of Intel and KLA-Tencor), which announced two products last November: InShape and OutPerform. InShape uses a nonlinear optical transformation algorithm to detect potential manufacturing failures during physical design to predict full-chip contour shape predictions across the process window. Using output from InShape, OutPerform takes timing, and place/route data together with encrypted fab technology files to identify timing and leakage parametric hotspots for violations due to systematic violations. The resulting timing optimization directive drives place/route tools.

While all fabs have their own DFM kit, what Clear Shape does, according to VP of marketing and business development, Nitin Deo, is to predict during the design stage how the ideal GDS shapes will print as contours in silicon. From that, designers can predict hot spots and parameter variations. “Most of our work is in creating those models and calibrating them to a particular silicon manufacturer’s backend process,” he noted.

The company claims that full-chip prediction of silicon contours across the process window can be done within eight hours for an 18mm x 18mm chip. Deo maintains that the company’s technologies are manufacturing/OPC tool agnostic, and that the contour predictions are >90% accurate between the ideal GDS shapes and silicon, regardless of which “in-between” OPC tool might have been used.

The company has been working with TSMC, UMC, IBM, Samsung, Chartered, NEC, and others to correlate its contour predictions to a specific fab’s silicon (i.e., calibrating the models). Deo told WaferNews that contour prediction calibration and hot spot detection correlation has been accomplished for several customers: TSMC (65nm and 55nm nodes done, 45nm to be released soon); IBM/Chartered/Samsung (65nm), and NEC (90nm is done; 65nm will be completed soon). STARC recently became a customer, and Deo said he can publicly identify ATI as a customer as well.

Making contour prediction the company’s mission arises from the reality that no matter what, as ideal GDS shapes go through post-GDS manipulations, contours on silicon are the end result, and they change with respect to process conditions. “Manufacturability involves predicting how those ideal GDS shapes will change into contours and how those contours will impact the chip performance,” he noted. Some of the problems encountered could result in either catastrophic failure or compromised chip performance (e.g., electrical, timing, power).

Deo also described for WaferNEWS what he calls the “variability challenge” — i.e., with each technology generation the variability in device performance increases, and the difference in variability is quite dramatic when going from 65nm to 45nm. “If you look at that 65nm and 45nm performance variation, there is overlap between the two — so if the best performance ‘corner’ of 65nm is the same as the worst performance ‘corner’ of 45nm, why would you go to 45nm?” he asked. “That means you are not getting the maximum value out of your process technology.” The answer is to control the variations, but that first requires that one can predict their causes, Deo said. “Then you can put some preventive measures into your design.” — D.V.