January 24, 2006 – Applied Materials Inc., Santa Clara, CA, and European R&D consortium IMEC have formed a joint effort to develop 32nm and 22nm-node copper/low-k interconnect processing technologies.

Under the agreement, IMEC will install Applied equipment to deposit Black Diamond II low-k film (k <2.5), a Reflexion LK CMP system for copper/low-k planarization with advanced process control and technology for polishing low-k dielectric materials, a Slimcell ECP system for profile control of copper critical layers, and Endura barrier/seed deposition system using ALD and PVD.

The work is part of IMEC’s nanoelectronics research platform, which includes leading chipmakers Infineon, Intel, Panasonic/Matsushita, Philips Semiconductors, Samsung, STMicroelectronics, Texas Instruments, and TSMC.

Dr. Luc Van den hove, IMEC VP of silicon process and device technology, said the joint effort will enable “world-class capability for developing the sub-32nm generation back end process flow.” The project is expected to start collecting 32nm data from the toolset by the end of 2006.

“This kind of expert collaboration is essential to better understand the complex interface engineering and circuit scaling issues that our customers will face with advanced technology nodes,” stated Farhad Moghadam, senior VP and GM of Applied Materials’ thin films group.