April 17, 2006 – Magma Design Automation Inc., Santa Clara, CA, has released a new “lithography-aware” product line aiming to automate IC design for 65nm- and below process geometries.

The Talus platform provides RTL-to-tapeout through a new IC implementation methodology, “Automated Chip Creation,” built on Magma’s unified data model architecture, which the company claims lets designers create flat or hierarchical layouts in just a few hours, beginning with as little as 10% of the design RTL available. The software automatically creates multiple floorplans with each subsequent RTL change to enable real-time viewing of their impacts on chip size.

A new constraint set, called “Relative Placement Constraints,” enables the user to reproduce desired aspects of a previous floorplan, and establish accurate timing constraints, investigate floorplan alternatives, and trade off package decisions with respect to design speed, area, noise, yield, and power integrity early in the chip design process. Automatically handling the production floorplan change minimizes the impact of late-arriving RTL and design requirement changes.

The software also incorporates sophisticated routing algorithms developed in conjunction with IBM and the U. of Bonn. Multithreading and distributed processing capabilities allows users to implement very large designs in as little as two days, the company claims.

Magma says full chip designs for various applications, ranging from 4 to 15 million gates, have been processed through the Talus flow. One early customer, NEC Electronics America, uses Talus for flat design methodologies of 12 million gate and larger chips, with overnight confirmation of the floorplans, according to John Fallin, executive director for NEC America’s custom SOC engineering unit.

One version of the Talus line, Talus LX, synthesizes chip RTL for timing, power, and placement constraints, and generates physical partitions for power and clock prototypes. Another product, Talus PX provides physical implementation of the design, including near abutment layout, final physical partitions, power and signal routing, and chip-level clock tree synthesis. Both products are currently in limited release, with production release scheduled for later this year.