By Phil LoPiccolo, Editor-in-Chief, Solid State Technology
The semiconductor industry needs to usher in a new era of “collaborative innovation” to push beyond the limits of classical scaling and achieve further advances in information technology price-performance ratios at the system level. That idea, proposed by opening keynote speaker Bernard Meyerson, IBM fellow, VP strategic alliances, and chief technologist at IBM’s Systems and Technology Group, kicked off the The ConFab on Monday, setting the tone for three days of top-level executive discussions on a range of issues facing chipmakers and suppliers alike.
Contrary to popular belief, classical scaling is not Moore’s Law, which is a law of economics — not a technical law — that speaks only to the density of components per integrated circuit, Meyerson explained. Rather, classical scaling is about making devices on an integrated circuit smaller, and it is defined as the synchronous reduction, year on year, of a fixed set of more than 20 device attributes — including not only physical measures of gate dimensions, gate oxide thickness, and so forth, but also factors such as power consumption — that govern the performance of silicon technology.
Unfortunately, classical CMOS scaling as we know it is dead, Meyerson said, because it results in unacceptable gate leakage, requires higher voltages for additional performance, and leads to a dramatic rise in power density. “The underlying problem is that atoms don’t scale,” he explained, pointing to the gate oxide in a CMOS circuit to illustrate the point. “In a modern scaled oxide that is only five to six atoms thick, it’s not going to be possible to scale that by a factor of two and get an oxide that’s only two or three atoms thick,” he said.
Furthermore, at the current scale, if we assume only one-atom high defects on each silicon layer, we find that a 33% variability will be induced. The bad news is that such single atom defects can cause local current leakage 10-100x higher than average, he said. The really bad news is that such non-statistical behaviors are appearing elsewhere in technology.
Therefore, while scaling is still viewed as a means to drive down costs, in the future, we can no longer view scaling as a means to drive processor-level performance, Meyerson noted. “The focus used to be on processor performance alone– but that game is over,” he said. Instead, we must turn to innovation to improve system performance, he asserted, and that speaks to a need for far better integration.
At the device level, there are several innovative approaches we can take, Meyerson added, including the use of strain-induced mobility improvements as well as novel materials and structures. Indeed, strained silicon is a key to enabling the next generations of CMOS. Tension enhances n-FETs, whereas compression enhances p-FETs, he explained, and the simultaneous integration of compressive and tensile strained layers has enabled significant optimization in IBM’s 90nm-node products that are currently shipping. In fact, from 1990-1994 alone, a 35,000% improvement was achieved in the electron mobility of silicon, a 40-year-old, supposedly mature material.
Innovations “far outside the box” include self-assembled nanotechnology-based devices such as vertical transistors using semiconductor nanowires and self-aligned carbon nanotube FETs with extension contacts based on charge-transfer chemical doping, Meyerson predicted.
He added that developers of nanotechnology “are creating a very fine art form” around the idea of self assembly. “This is important because if a layer is too small for you to build it on your own, then the layer is going to have to build itself,” he said. “To make our way to the future, we’ll have to make materials do our work for us.” Other items on the “innovation driven “device roadmap” include ultrathin silicon-on-insulator (SOI), high-k gate dielectrics, double-gate CMOS, and FinFET technology.
Innovations in interconnect techniques will likewise entail developments beyond traditional scaling, Meyerson claimed, and will include significant advances in backend-of-line (BEOL) technology, as well as in novel materials, processes, and structures, Meyerson claimed. As an example, he showed that on the innovation-driven “interconnect roadmap,” the k–eff values of inter-metal dielectrics are estimated to drop from about k=2.4 in 2007 to k=1.9 by 2010 to k<1.3 by 2020, through the development and application of porogen and air-gap techniques.
While improving such individual technologies will be vital, a “holistic design,” integrating innovations in everything from atoms to software, would provide the most effective means to optimize the value of IT offerings to the end user, Myerson contended. Such an approach, he pointed out, would involve the simultaneous optimization of materials, devices, circuits, cores, chips, system architecture, system assets, and system software.
Optimizing value will also require collaborative partnerships. The recently developed Cell-based computer system, jointly developed through IBM’s partnership with Sony and Toshiba, serves as prime example, he said. This system chip features 234 million transistors on eight synergistic processors, and performs 256 billion floating-point operations/sec. It’s not just investment in capital that makes such collaborations work, Meyerson said — it is perhaps, more critically, the aggregation of intellectual capital that drives progress.
Alas, innovations are expensive, Meyerson said, citing the huge costs associated with advances in lithography (moving from dry to immersion to EUV), in transistors (moving from silicon to strained silicon, high-k gate dielectrics, double gates, and fin-FETs), in interconnects (moving from traditional to ultralow-k porous and air-gap dielectrics), and in manufacturing (moving from high-volume to on-demand lot sizes). “Every one of these innovations costs a fortune,” he said.
“A funny thing happened on the way to the future — we went broke,” Meyerson said. “I can remember when a new fab used to cost a million dollars. Today, a new fab requires investment of some $4 billion, which is more than the GNP of a small country.”
To meet technical challenges through traditional approaches, semiconductor R&D expenses would have to increase at a rate of some 12.2%/year through 2020, but revenues would grow only 6.5% during that same period, Meyerson showed, referring to a now famous chart from VLSI Research. “This is the industry trend as of today,” he said. “But it is not sustainable, and will not and must not happen.”
The answer, Meyerson believes, is to continue the trend toward a “globalization of semiconductor R&D.” This is already a pervasive strategy thanks to a global recognition of the challenges facing the semiconductor industry, he said. For example, IBM has a very large consortium going with Sony, Samsung, Toshiba, AMD, Chartered, and Infineon. This and other consortia, including SELETE, SEMATECH, and IMEC, are the beginnings of collaborative innovation on a broad scale. The participants are competitors, he said, but pre-competitive research “is so expensive that if we don’t work together, we won’t survive.”
“Basic research has been centralized to jointly operated government and/or industrial laboratories, enabling an era of pre-competitive cooperation,” Meyerson said. “This is here. And it’s going to grow rapidly.”
Collaborative innovation is the key strategic imperative and a “new lever” in information technology development, Meyerson noted. “We are seeing the first emergence of open standards and technology ecosystems, enabling collaborative innovation in what was a highly proprietary endeavor.”
Innovation and integration deliver what scaling can’t, Meyerson concluded, noting that high-frequency systems at high functionality have been demonstrated through holistic design. System solutions optimized via holistic design will ultimately dominate progress in information technology, he added, and fiscal reality is driving the industry toward consolidation around innovation networks, which will require the globalization of technology ecosystems. — P.L.