September 6, 2006 – Chinese foundry Semiconductor Manufacturing International Corp. (SMIC) has developed a low-power digital reference flow for its 90nm process technology with Cadence Design Systems Inc. The flow is a complete RTL-to-GDSII, low-power flow focused on efficient energy utilization for 90nm system-on-chip (SoCs), to address nanometer design challenges such as low power, complex hierarchical designs, timing, and signal integrity signoff. It addresses hierarchical block partitioning, physical timing optimization, 3D RC extraction, IR drop, leakage and dynamic power optimization, crosstalk glitch, and delay analysis, according to the companies.

SMIC also has completed a standard design platform with VeriSilicon Holdings Co. Ltd. for its 0.13-micron low leakage process, proven in silicon through a shuttle prototyping service. The process includes memory compilers for single port and dual port SRAM, diffusion programmable ROM, two-port register file compiler, and standard cell and I/O libraries. End-use products include battery-powered applications such as handheld devices.