October 29, 2009 – Intel and Numonyx say they have built a "vertically integrated" 64Mb test chip enabling stacking of multiple layers of phase-change memory (PCM) arrays within a single die, paving the way for devices that can scale well beyond conventional memory with more capacity, lower power consumption, and taking up less space.

Memory cell architectures incorporate arrays of cells with a stacked storage element and selector. In their work, the researchers layered a PCM element with a thin film, two-terminal "ovonic threshold switch" (OTS) as the selector, in a true cross point array; the OTS matched physical and electrical properties for PCM scaling, and multiple layers of such cross point arrays can be stacked over CMOS circuits for decoding, sensing, and logic functions, they noted in a statement.

Greg Atwood, senior technology fellow at Numonyx, called the results "extremely promising," noting that they show "potential for higher density, scalable arrays and NAND-like usage models."

"We continue to develop the technology pipeline for memories in order to advance the computing platform," added Al Fazio, Intel Fellow and director of memory technology development.

Intel and Numonyx will discuss their work in a co-authored paper at next month’s 2009 International Electron Devices Meeting (IEDM) in Baltimore, MD.