by Franklin Kalk, CTO, Toppan Photomasks
September 18, 2009 – Most rational people would agree that the use of "nano" as a prefix for products covering everything from sandpaper to acne creams is…well, irritating. How long will we have to wait before "nano" goes away or an application truly deserving such prefixion emerges? Those attending the SPIE/BACUS conference on photomask technology in Monterey, CA (Sept. 14-17) recently may have finally witnessed that emergence.
Spanning four sessions and more than 15 papers, people representing both the hard-disk and IC industries mapped out the intersection of nanoimprint lithography (NIL) and patterned hard-disk media. Those from the IC side felt right at home watching every hard-disk media presentation flashing the same roadmap ("ad nauseum," as one presenter put it). And those from the hard-disk side must have felt comfortable surrounded by a lithography community that has never met a patterning challenge it couldn’t solve.
And what an interesting challenge this is. The hard-disk roadmap calls for recording media to move from planar to grooved surfaces (so-called discrete track media) to individually defined magnetic dots (bit-patterned media) over the next few years. Bit densities will exceed a terabit/in2 in the same timeframe, requiring individual magnetic dots with dimensions of 10-20nm on a side. The bit density roadmap seems daunting at first, but it is balanced by the patterns’ simplicity and defect tolerance.
While not evenly split among the four sessions, paper topics could be divided roughly into the following categories: patterned hard-disk media, master template fabrication, defect management, and metrology. In the first session (Tues. 9/15), the three dominant hard-disk drive companies and a storage-system integrator presented largely coincident overviews of patterned disk media and the associated manufacturing challenges. Pete Goglia of Xyratex International noted that the disk drive market is fueled by the growth of digital content, whether it’s being created, delivered or stored. Bit growth is >50% CAGR, and with fixed-drive form factors and drive units growing about 15% annually, the balance is covered by bit density growth. To effect today’s 300Gb/in2 density, modern drives employ perpendicular recording and tunneling giant magnetoresistive read heads. According to Tom Albrecht of Hitachi Global Storage Technologies, somewhere just south of 1Tb/in2 media patterning will be needed to constrain the individual magnetic features to avoid thermal instability and maintain SNR. A single magnetic island comprising what he termed a "thermal stability unit" contains multiple magnetic grains (each about 6nm in size) and is more stable when separated from other islands by nonmagnetic material. Constraining those islands in one dimension with grooved media affords a density gain of perhaps 30%. A much greater gain of 5×-10× is realized by bit patterning, in which each island is a spatially distinct magnetic dot. Patterning 15nm dots over multi-square-inch surfaces at hundreds or thousands of parts per hour for about a dollar a disk narrows the lithography field to one candidate: nano-imprint lithography. Henry Yang of Seagate Technology noted that conventional semiconductor lithography simply won’t work. NIL’s attributes (including double-sided printing), which are often incommensurate with semiconductor manufacturing, can be advantages in patterned media manufacturing.
In NIL, a master pattern is replicated as many as 10,000 times, and each replicate can itself be replicated, again as many as 10,000 times, into a loyal image of the master. The final image on the disk is a relief pattern in a photosensitive material. In principle, a master’s patterned groove or bit structure can thus be propagated to as many as 10 million disks. Since NIL is a 1X lithography, the master patterning tool must have excellent resolution. Rotary-stage electron beam tools fill this bill nicely for patterned media, but they are slow (weeks to write a single master). Writing speed is a critical issue in IC photomask production, but the small number of disk formats (or tapeouts in semiconductor lingo) favors replication speed over mastering speed. And e-beam patterning time can be shortened by patterning a sparse feature population and filling in the rest with directed self-assembly using block copolymers.
It should be noted that none of the speakers said patterned media was a done deal, and there are alternatives — notably heat-assisted magnetic recording, which can in principle be combined with patterned media to extend density yet again. Remaining unanswered questions appear to center on the behavior of the magnetic islands, not on the efficacy of NIL; these will probably be answered within the next year. Assuming magnetic films can exhibit adequate recording properties when patterned into such miniscule features, NIL’s future could be bright indeed.
Can nano-imprint lithography succeed in IC manufacturing?
For years, the NIL community has had difficulty gaining traction in semiconductor manufacturing, with key technical issues involving template writing speed and defect management. Defect inspection and repair were the subjects of several papers at BACUS/SPIE.
It has been clear for some time that electron beam-based inspection is the desired solution for NIL templates. Dai Nippon Printing and Hermes Microvision showed results of their cooperative work using the Hermes eScan e-beam inspection tool to detect defects on 22nm NIL templates. Naoya Hayashi presented DNP’s latest patterning results using both 50 keV and 100 keV electron beam writing tools. Using high-resolution, low-sensitivity resists, DNP has steadily pushed the resolution of its 50 keV variable-shape, beam-writing process, now capable of sub-25nm lines and spaces. Although much slower, the 100 keV Gaussian spot process has achieved 14nm lines and spaces.
DNP applied its patterning processes to build a programmed defect mask. Such masks, consisting of basic patterns into which various types of defects are intentionally written, are commonly used in IC photomask manufacturing to evaluate and verify inspection-system performance. The mask was then inspected with the Hermes eScan, which could capture defects around 15nm programmed size. Hayashi-san pointed out that the patterning process had difficulty resolving small defects, and the defects were not rigorously sized by a separate technique. As with any inspection tool, smaller feature sizes are harder to detect than larger features, and the sensitivity was lower on the smaller patterns.
Hong Xiao of Hermes gave a separate paper on the use of the eScan to inspect imprinted wafers. The prints were from the DNP programmed defect mask, limited to 32nm minimum feature size. As with the template inspection, all defects larger than 15nm programmed size were captured regardless of pattern type, confirming the technical feasibility of this technique for inspection at advanced nodes. Still, the main issue with e-beam inspection historically has been speed, and the eScan is no exception: scan speed is <1 cm2 per day, about 50× slower than conventional mask inspection when scaled for the mask magnification difference. Xiao did not provide a roadmap, so it’s difficult to predict how far e-beam inspection speed and sensitivity can be extended.
Because the NIL template impresses a relief structure into a photopolymer on the wafer, the template features must have consistent height as well as proper CDs and placements. Marcus Pritschow of Carl Zeiss SMS described the company’s effort to meet this height-control requirement with its electron beam repair tool. Using both SEM review and actual imprints, Pritschow showed that timed deposition and etching are adequate to reconstruct missing template features or to remove unwanted material. The extremely small features of the 1X template require better stage and beam stability and better repair resolution than currently necessary for 32nm 4X masks, and the Zeiss test stand looks like an excellent start toward a viable template repair tool.
It’s encouraging to see effort on NIL template inspection and repair. With 32nm logic entering production within the next year and 22nm test chips in the hopper, these demonstrations of 22nm inspection and repair feasibility are none too soon. Nobody knows if or when NIL can be successfully applied to semiconductor manufacturing — but template repair is in good hands, and we’ll be waiting for a while for inspection viability.