June 20, 2008 – Toshiba and IBM say they have developed a higher-performance CMOS FET by increasing device-channel hole mobility through a modification of direct silicon bonding (DSB), a hybrid of (100) and (110) substrates (Figure 1), rather than new materials such as high-k and metal gates and new structures.

Figure 1: Two silicon crystal face. (Source: Toshiba)

The firms say their new methodology works by rotating the plane of the (100) layer of a silicon wafer by 45° and thinning the DSB layer of the (110) substrate (Figs. 2-3). The resulting integrated technology offers 10% improved delay of the ring oscillator compared with conventional DSB substrate 0° (100) wafers which bond (100) and (110) substrates to the wafer, and ring oscillator delay was improved 30% vs. the standard (100) wafers (Fig. 5) Further integration can push to even higher advances.

Figure 2: Two types of DSB wafers. (Source: Toshiba)

Figure 3: Process Flow of DSB wafer fabrication. (Source: Toshiba)

Hole mobility in positively-charged field effect transistors (pFETs) can achieve higher performance on a substrate with (100) surface orientation than on a substrate iewth (110) surface orientation. For nFETs, though, electric charge mobility deteriorates on a (110)-oriented substrate vs. mobility on a (100)-oriented one, the firms explained in a statement. Their new achievement uses hybrid orientation tehnology fabricated on a hybrid substrate with different crystal orientations to achieve “significant pFET performance without any deterioration in nFET performance.”

Figure 4: Cross section of defection. (Source: Toshiba)

Figure 5: Thin DSB wafer demonstrates 11% faster ring oscillator speed vs. thick DSB wafer, and 30% faster over (100) bulk. (Source: Toshiba)