December 8, 2011 – Marketwire — SuVolta Inc., developer of scalable low-power CMOS technologies, revealed its Deeply Depleted Channel (DDC) low-power transistor technology at IEEE’s International Electron Devices Meeting (IEDM) 2011 this week in Washington DC. Part of SuVolta’s PowerShrink low-power CMOS platform, the compatible planar bulk CMOS-based process technology reduces power consumption by 50% without slowing operating speed, and can be implemented in existing fab facilities and CMOS processes.
The technology can bring semiconductor device scaling below the 20nm node, said Dr. Bruce McWilliams, president and CEO at SuVolta, by reducing threshold voltage (VT) variability and enabling continued CMOS scaling. Advanced voltage scaling techniques could bring the DDC power reduction effect to 80%.
When a voltage is applied to the gate, a deeply depleted channel forms, typically with several regions — an undoped or very lightly doped region, a VT setting offset region and a screening region. The undoped or very lightly doped region removes dopants from the channel, cutting down on random dopant fluctuation (RDF). This allows VDD scaling and better mobility. The VT setting offset region sets the transistor threshold voltage levels, without degrading channel mobility. This region also improves sigma VT over conventional transistors, SuVolta reports. The screening region screens the charge and sets the depletion layer depth. It also serves as a body for dynamic VT adjustment through biasing, if desired.
Benefits include:
- 30% lower operating voltage with no performance impact;
- lower leakage;
- multiple VTs in designs for low-power products;
- less design "guard banding";
- improved yields;
- increased channel mobility for increased drive current;
- reduced drain induced barrier loading (DIBL); and
- increased body coefficient for better VT control.
Dr. Scott Thompson, CTO at SuVolta, expects 28nm and 20nm "will be long-lived nodes," because chip-fab costs are plateauing. Mobile-application chips require cost control and low power consumption, he added. DDC is fully compatible with today’s CMOS processes and fab facilities, allowing semiconductor companies to retain their existing circuit intellectual property, he said.
Also at IEDM, Fujitsu Semiconductor Limited and SuVolta Inc. presented ultra-low-voltage operation of static random access memory (SRAM) blocks down to 0.425V by integrating SuVolta’s DDC into Fujitsu Semiconductor’s low-power process technology. The two companies have verified that a 576Kb SRAM can work well at approximately 0.4V by reducing CMOS transistor threshold voltage (VT) variation to half. This technology matches well with existing infrastructures including existing system-on-chip (SoC) design layouts, existing design schemes such as body bias control, and existing manufacturing tools.
See a slideshow of 10 IEDM paper sneak-peeks here.
An implementation of SuVolta’s DDC transistor on Fujitsu Semiconductor’s low-power CMOS process is shown in Figure 1. The cross sectional transmission electron micrograph (TEM) shows the transistor fabricated on a planar bulk silicon structure.
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| Figure 1. SuVolta’s cross-section TEM |
The yield is calculated by counting macros in which all bits have passed.
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| Figure 2. Yield of 576k SRAM macro as a function of supply voltage. |
View video and read about SuVolta’s Deeply Depleted Channel structure at www.suvolta.com/cmos-power/.
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| Figure 3. SuVolta’s DDC technology. |
Fujitsu Semiconductor is going to advance the technology and aggressively respond to customers’ requests for low-power consumption and/or low voltage operation in consumer products, mobile devices and other offerings.
Fujitsu Semiconductor Limited designs, manufactures, and sells semiconductors. For more information, please see: http://jp.fujitsu.com/fsl/en/.
SuVolta, Inc. develops and licenses scalable semiconductor technologies that enable a significant reduction in IC power consumption while maintaining performance. For more information, visit www.suvolta.com.