by Richard Lewington, Applied Materials
May 26, 2011 – Sixty years ago, a state-of-the-art memory device was a tube full of mercury, with 500 bits of data stored as acoustic waves travelling up and down between transducers at either end. Today, flash memory cards containing more than 100 billion bits can be found at the supermarket, next to the chewing gum. Computer memory has come a long way, but can it keep going?
A prestigious panel of experts explored this topic at the 2011 IEEE International Memory Workshop in Monterey, California. Speaking to a large audience of over 300 technologists, the panel featured experts representing key players in the memory industry, from research institution imec, memory makers Hynix, Samsung and Toshiba, to memory consumer Nokia.
What do the rapid changes in our society — mobility, pervasive connectivity, and disruptive applications such as Netflix — mean for the memory device technology enabling these changes, inquired moderator Raman Achutharaman (from event sponsor Applied Materials)? The panel’s surprising answer: maybe not much, at least at the fundamental level where each bit of information is stored. DRAM (or "execution memory" as Nokia’s Matti Floman put it) will retain the same basic transistor/capacitor structure for many more years, while "mass memory" will remain NAND flash, employing the floating gate memory cells that have served us so well for more than 20 years.
It seems almost sad that elegant alternative cell technologies such as spin-transfer torque RAM (STT-RAM), which promises to unify execution and mass storage into the Holy Grail, a "universal memory," are left waiting in the wings, while chipmakers will typically choose the evolutionary path, where one exists. Cost and uncertainty mean that revolutionary developments will only happen when no other avenue is available.
However, paradoxically, this pragmatic conservatism is driving a remarkable breadth of ingenious new ways to increase cell density in two dimensions. Sung-Kye Park, research fellow at Hynix Semiconductor, described the use of air gaps to combat cross-communication between cells. Techniques such as atomic layer deposition (ALD), once the preserve of physicists and materials scientists, are becoming as commonplace as chemical and physical vapor deposition (CVD and PVD). Yoshitaka Tsunashima, GM at Toshiba’s device process development center, pointed to the announcement last month of an "ordinary" floating gate device with 19nm design rules, a remarkable achievement.
Many people have asked whether DRAM scaling below 20nm is possible. Jooyung Lee, principal engineer at Samsung Electronics working in DRAM core technology, pointed out that the industry has asked itself that question at every node, yet DRAM technology has tracked Moore’s Law for decades, doubling density every two years. New materials remain the key enabler for future development, asserted Laith Altimime, director of memory scalability and extendibility at imec, but with a new focus on "stack engineering" — the interaction of materials at interfaces, not just the individual materials, is an area of intense research.
A common challenge facing all memory devices is lithography. How can such infinitesimal circuits, far below the 193nm wavelength of conventional scanners, be patterned on the wafer? Extreme ultraviolet lithography (EUVL), with a 13.5nm wavelength, perhaps the natural replacement for optical lithography, has been "just around the corner" for fifteen years, but is still not ready for mass production.
With EUVL mired in development, chipmakers have reluctantly adopted double-patterning techniques, where conventional lithography is combined with extra processing steps to produce smaller features. But what’s next? Some are exploring triple- or even quadruple-patterning, a painfully long process that introduces new challenges in controlling the multiplication of patterning errors. However, each unit process in multiple patterning is well-characterized using proven tools with high throughputs. In a telling sign that EUVL may already be obsolete, Tsunashima-san indicated that Toshiba is exploring the possibility of combining EUV with double patterning. That would be a bold move, indeed.
3D NAND flash memory sidesteps traditional scaling, increasing cell density by stacking cells vertically rather than shrinking the cell dimension. Because the individual cell size does not need to scale horizontally, vertical NAND arrays avoid the lithography issue. However, the date at which these devices will enter mass production is becoming less clear. The challenge of achieving high yield and low cost while fabricating all those extra layers can be as much of a burden as quad patterning! Which route to choose is an unenviable decision facing memory makers today. Tsunashima-san said that Toshiba is pursuing 3D as a kind of insurance, ready to push to mass production when FG eventually runs out of steam. Hynix’s Park was more definite, predicting an insertion point in 2013, with a running figure leaping over a brick wall representing the end of planar scaling.
From the memory consumer perspective, Nokia’s Floman said that the pace of development in smartphones, for example, is so rapid that they need "standard solutions," where the complexities of individual technologies are hidden from the end user, with built-in control systems so that memory modules adhere to emerging high-performance standards.
Two dimensions or three, evolution or revolution, the memory industry stands ready to meet the challenges posed by the insatiable demand for faster, cheaper, more reliable memory to power the mobile supercomputers that more and more of us keep in our pockets.
Richard Lewington is a writer in Applied Material’s Technical Communications group, focusing on bringing Applied’s diverse technology to the outside world. He holds a master’s degree in mechanical and electrical engineering from the University of London.