April 20, 2012 — Researchers sponsored by Semiconductor Research Corporation (SRC), a university-research consortium for semiconductors and related technologies, have identified a path to overcome challenges for scaling multi-core semiconductors by addressing how to scale memory communications among the cores. The results can lead to smaller integrated circuits (ICs) into computer hardware without all-new software development.
Professor Daniel Sorin from Duke University, Professor Milo M.K. Martin from University of Pennsylvania, and Professor Mark D. Hill from University of Wisconsin performed the SRC-guided research on extending the path for cores to communicate by reading and writing to a shared space, or cache-coherent shared memory. In each core, one or more caches hold the subset of memory locations that most recently were written and read by the core.
Cache coherence protocols are built into hardware so that each cache and memory controller can access shared data at high performance. As computational demands on the cores increase, protocols must remain fast and energy-efficient, even with multiple cores.
The research could prevent radical changes in computer programming, maintaining the mainstream technique of cache-coherent shared memory, but also facilitates backward compatibility with the vast amount of legacy code written for cache-coherent shared memory. “We have refuted calls for a radical design change by showing that, using already existing techniques, we can create cache coherence protocols that scale to hundreds and perhaps even thousands of cores,” said Sorin.
“Our results allow us to confidently predict that, with these new protocols, on-chip coherence is here to stay. Computer systems don’t need to abandon current compatibilities to accommodate even hundreds of cores,” Sorin added. “Chip area and energy consumption may limit future multi-core chips, but our research refutes conventional wisdom that multi-core scalability of the memory system would be the primary scaling bottleneck.”
The alleged lack of scalability of coherence is attributed to the poor scaling of the storage and traffic on the interconnection network that coherence requires, as well as concerns about latency and energy needs. The industry has questioned if future multi-core chips will be able to rely on coherence, or if they will communicate with software-managed coherence or message passing that does not share memory. These new alternatives bring high costs.
This research brings together existing techniques for creation of shared caches augmented to track cached copies, explicit cache eviction notifications and hierarchical design. Scalability analysis of this design confirms that shared memory among multiple cores and its benefits for future computational increases can allow a broad range of technologies and industries to maintain their reliance on more powerful, cost-effective roadmaps. “Chipmakers are not operating in a vacuum and must continue to identify how they’ll enable their partners on the hardware side,” said SRC EVP Steven Hillenius.
SRC defines semiconductor industry needs, invests in and manages the research that gives its members a competitive advantage in the dynamic global marketplace. For more information, visit www.src.org.