January 2, 2012 —  In 2011, the hot topic was whether semiconductor manufacturing would move to metal gate first or gate last. Today, this is still a hot topic, although I posit that everyone will use gate-last manufacturing at 20nm. Currently, 22nm is in production at Intel, the first company to implement gate last; others such as IBM and foundries like TSMC will also use it for 20nm manufacturing.

20nm manufacturing will be very difficult, which could extend the period for 28nm. A mid-node may be developed or a “loose 20nm structure,” because of the difficulty in obtaining acceptable yields. Essentially, we are at 28nm now and using gate first or gate last, but the industry will shift to a 20nm metal gate last approach, exclusively.

Gate first is similar to silicon gate technology because it is very extendable and very transferable from existing silicon gate technology. Gate last is very difficult because it is a completely new process structure using multiple film stacks. The focus for 20nm or a mid-node will be to drive improved device performance primarily for consumer products and that, in conjunction with technologies like laser spike annealing, will provide the optimum battery life.

For junction formation and leakage, there is a growing set of problems caused by using older technologies. As we progress to smaller features, laser annealing plays a much more important role in the structure’s performance by significantly lowering leakage. In addition, at these leading-edge device nodes, bump packaging, or flip chip, enables increased device performance while reducing the total package form factor by utilizing through silicon vias (TSV) for 3D stacking. At 20nm, over 90% of leading-edge logic chips will require bump packaging solutions. Memory companies are aggressively pursuing TSV technology to bring it to mainstream DRAM production for memory-on-memory technology in the next two years. In addition, silicon interposer solutions are gaining traction and I believe that at some version of the 28nm logic node, companies will use wafer foundries with silicon interposer technology to provide high-density wire interconnection. Packaging in general used to be driven by logic and the computing market segment. Moving forward, bump packaging will play an increasing role as we transition from laptops to tablets and from on-board disk drives to cloud networking. These devices will drive the change in technology.

With the many technology transitions that need to occur to move to the 22/20nm node, the transition to TSV 3D will ultimately decide the winner for the balance of this decade. Also, compounding the equipment manufacturers’ R&D investments will be the transition to 450mm diameter wafers, which will be driven by all the major semiconductor companies. By combining the technology challenges we face and the wafer diameter change, executives in the equipment industry will require a strong balance sheet to be successful.

Art Zafiropoulo is chairman and CEO of Ultratech Inc.

This article is part 7 of a series of 22nm forecasts from Solid State Technology contributors.

Part 1: Semiconductor process technology challenges at 22nm by Dean Freeman, Gartner

Part 2: At 22nm, leave chip layout to the experts by Gary Smith, Gary Smith EDA

Part 3: Focus on first order effects at 22nm by Howard Ko, Synopsys

Part 4: Mask-wafer double simulation: A new lithography requirement at 22nm by Aki Fujimura, D2S

Part 5: 22nm requires foundry-to-packaging-house cooperation by E. Jan Vardaman, TechSearch International

Part 6: Strained silicon and HKMG take the stage at 22nm by Mohith Verghese, ASM America

Part 8: Startups pave the way to CMP at 22nm by Michael A. Fury, Techcet Group

Part 9: 20nm mask technology relies on SMO and DPT by Franklin Kalk, Toppan Photomasks

Part 10: 3D integration key to 22nm semiconductor devices by Paul Lindner, EV Group