April 10, 2012 — The 2012 Symposia on VLSI Technology and Circuits, June 12-14 (Technology) and 13-15 (Circuits), will take place in Honolulu, HI, with microelectronics manufacturing and circuit development research presentations. To foster joint interactions among device technologists and circuit/system designers, the technical programs of both symposia will overlap this year, and joint focus sessions on important topics will be held for the first time in the Symposia’s history.
More than 200 presentations will be given for approximately 1000 attendees. Short courses will occur prior to each symposium, with invited speakers addressing the industry’s most important issues. Evening rump sessions will spane a range of topics at the leading-edge of technology and circuit design. The VLSI Technology Symposium will be preceded by a satellite Silicon Nanoelectronics Workshop on June 10-11.
CMOS scaling and new 3D memory structures are highlights at this year’s Symposium on VLSI Technology, said Ming-Ren Lin, GLOBALFOUNDRIES, and General Chair.
The VLSI Circuits program will cover intelligent automotive vision systems, medical electronics, and diverse other applications, said Ajith Amerasekera, Texas Instruments, and General Chair, adding that more “universal topics” will also be covered, such as energy-efficient electronics and wireless communications interfaces.”
Short Courses
VLSI Technology Short Course (June 11), 14nm CMOS Technology & Design Co-Optimization and Memory. This course will comprise 6 lectures given by distinguished speakers, covering state-of-the-art technology and circuit design for 14nm-generation CMOS.
VLSI Circuits Short Courses (June 12) — Two parallel full-day courses will be given by 12 distinguished international speakers from industry and academia.
– Designing in Advanced CMOS Technologies
– Ultra Low Power SoC Design for Future Mobile Systems
A single registration fee covers both, and participants can switch between the two. Afterward, a roundtable for both Circuits Courses will be held to foster interaction and discussion with all speakers.
New VLSI Symposia Technology/Circuits Joint Focus Sessions
The new Technology/Circuits Joint Focus Sessions are devoted to advanced device and circuit design co-optimization, a key ingredient for future progress.
– Memory (Wednesday morning, June 13)
– 3-D System Integration (Wednesday afternoon)
– Emerging Non-Volatile Memory (Wednesday afternoon)
– Advanced SRAM (Thursday morning, June 14)
– Design in Scaled Technologies (Thursday morning)
– Design Enablement in Scaled CMOS (Thursday afternoon)
– Embedded Memory (Thursday afternoon)
The Symposium on VLSI Technology will hold a special focus session Tuesday afternoon, June 12 on Low-Power and Steep Subthreshold Technology. The Symposium on VLSI Circuits will hold a special focus session Friday morning, June 15, Flash Memory.
Plenary Sessions
The Symposium on VLSI Technology will open with two invited plenary talks. First, Mike Mayberry of Intel will share his view through the “fog” of CMOS technology scaling, and identify directions for novel switching devices and new methods for computation. Then, Prof. Ichiro Yamada of the University of Tokyo will describe how advances in information and communication technologies and micro-electro-mechanical devices (MEMS) can be leveraged to address the rapidly growing issues of the aging population and lifestyle-related diseases.
The Symposium on VLSI Circuits will open with two invited plenary talks by renowned experts. The Evolution of Next Generation Data Center Networks for High Capacity Computing will be given by Nicholas Ilyadis, Vice President & CTO of the Infrastructure and Networking Group at Broadcom. He will discuss the challenges of modern cloud computing and how they can be resolved by redefined network topologies and their underlying technologies and silicon solutions. The second plenary talk, Technology Innovations for Smart Cities, will be given by Akira Maeda, Chief Technology Officer, Infrastructure Systems Company, Hitachi, Ltd. He will discuss the technology innovations needed to realize “smart” cities, with emphasis on applications such as sensing, highly parallel processing, and mobile broadband communication for sophisticated social infrastructure systems.
Evening Rump Sessions
The Symposium on VLSI Technology will hold two rump sessions in parallel on Tuesday evening, June 12 to foster open discussion of challenging R&D issues.
– Evolution of FinFET and Beyond? moderated by G. Yeap of Qualcomm and Y. Miyamoto of Tokyo Institute of Technology, will deal with the future of FinFET and other advanced transistor designs, such as ultra-thin body and ultra-thin BOX SOI, Ge and III-V transistors, tunnel FETs and other concepts.
– Patterning in Non-Planar World — EUV, DW or Tricky-193? moderated by G. Vandenberghe of IMEC and M. Tomoyasu of Tokyo Electron, will debate the future of patterning technologies.
The Symposium on VLSI Circuits also will hold two parallel rump sessions, on Thursday evening June 14.
– Is VLSI Innovation Dead? will feature seven experts (from IBM, Intel, AMD, NTT, and MIT, Shizuoka and Stanford Universities) discussing why companies in fields such as web software or server/OEMs are in the headlines, while semiconductor companies are noticeably absent. In short, the question for discussion is, is VLSI semiconductor innovation fine, dead, dying, or does it just need a kick-start?
– Will the Future Have More Analog or Digital Processing? Panelists from Analog Devices, Broadcom, Renesas Electronics, Xilinx, UC-Berkely and University of Tokyo will discuss whether the overall trend to digital circuit implementations is irreversible, or if the push toward digital circuits replacing analog counterparts is already finished. Digital circuits at new technology nodes don’t exhibit the same energy scaling as in the past, while analog-to-digital converter energy efficiency, for example, has improved more than 500-fold in the last decade.
A joint rump session will take place on Tuesday evening, Scaling Challenges Beyond 1xnm DRAM and NAND Flash Revolution?, moderated by R. Shrivastava of SanDisk and N. Lu of Etron. It will give the audience an opportunity to learn about future directions and issues for advanced memory technologies, including DRAM and NAND flash. The organizers of the VLSI Technology rump sessions (Thomas Skotnicki – STM and Katsura Miyashita – Toshiba) and of the VLSI Circuits rump sessions (Mark Bauer – Micron and Nicky Lu – Etron) invite all attendees of both VLSI Symposia to participate.
Luncheon
On Thursday, June 14, a luncheon sponsored by both Symposia will feature Nano-Satellites, CubeSats, and the Next Space Generation by Prof. James Cutler of the University of Michigan. He will discuss recent exciting trends in the space community, which are opening up access to space and sparking a wide variety of innovation globally. His talk will include stories of success and failure, and corresponding emerging challenges for the VLSI community will be highlighted.
Banquet
On Wednesday evening, June 13, a joint banquet will be held to provide an informal, relaxed atmosphere for information exchange between technologists and circuit designers.
The VLSI Technology Symposium began in 1981, while the VLSI Circuits Symposium was added in 1987. The two meetings have been held together ever since, rotating annually between Japan and Hawaii. The VLSI Technology Symposium is sponsored by the IEEE Electron Devices Society and the Japan Society of Applied Physics, in cooperation with the IEEE Solid State Circuits Society. The VLSI Circuits Symposium is sponsored by the IEEE Solid-State Circuits Society and the Japan Society of Applied Physics, in cooperation with the Institute of Electronics, Information and Communication Engineers and the IEEE Electron Devices Society. Visit www.vlsisymposium.org