By Manish Ranjan, Ultratech Inc.
Leading-edge consumer electronic products demand innovative silicon and packaging solutions. While front-end silicon technologies have progressed at a pace defined by Moore’s Law, the back-end infrastructure has lagged in similar advancements. This has created an interconnect gap whereby the signal speed achieved on the silicon side is significantly higher than the speed achieved on the printed circuit boards. Innovative solutions such as fan-out wafer-level packaging (WLP) technology deliver robust packaging solutions to meet the performance and reliability requirements for wireless chips. This article discusses the key demand drivers and packaging technology requirements for the mobile market segment.
Despite the recent economic outlook, it is anticipated that cell phone shipments in 2009 will exceed one billion units1. Of particular interest is the increase in shipments of smart phones. This segment has witnessed a steady increase in adoption of various features such as cameras, global positioning systems (GPS), and mobile TVs. Furthermore, features that were introduced at the high-end of the market migrate rapidly to other segments driven by aggressive price reductions. To effectively address the performance and form factor considerations, leading-edge IC suppliers have migrated to tighter design rules. However, there has not been a similar technology scaling effort in the back-end and printed circuit board area. While near-term packaging requirements have been met via incremental improvements of current packaging methods, new packaging solutions are being developed to meet the device scaling requirements.
Historically, wire bond packaging was widely utilized for connecting the silicon chips to the mother board. However, poor electrical speed and dense wire routing considerations do not render this packaging method effectively suited for leading-edge devices. Traditional WLP solutions are fan-in solutions and are limited to small die sizes. The introduction of fan-out WLP technology addresses the pad limitation consideration with traditional WLP, while delivering miniaturization and potential low-cost packaging advantages. In addition, fan-out WLP technology can effectively leverage current flip chip and WLP equipment infrastructure, thereby creating a cost-effective technology solution.
A key process step for fan-out technology is the reconfiguration of probed good die to sacrificial carrier. Once the panel fabrication is completed, thin-film technologies such as sputtering, photolithography, and electroplating are performed. The final interconnect process step is the ball drop process followed by package singulation and testing2. Die positioning control within the mold compound on the panel is one of the key factors affecting downstream process requirements. Unlike a typical silicon wafer, the die within the reconstituted wafer are not positioned in an accurate systematic array. The locations of the chips have a random error component due to the accuracy of the pick and place tool, and due to the shrinkage of the molding compound material during the compression molding process.
While considerable improvements have been made with pick and place equipment, it is very difficult to control the random shift of die during the compression molding process. This creates significant challenges in aligning subsequent metal layers to the device contacts. As such, it becomes extremely difficult to use a contact/proximity aligner with two-point global alignment methodology and expose the entire panel. While using aligners during exposure of fan-out panels, some device manufacturers are introducing chip designs with large passivation openings to accommodate the overlay error. However, it becomes cost prohibitive to utilize such an approach in large volumes.
The use of 1X stepper technology enables customers to use an enhanced global alignment routine whereby they can select multiple die to create an alignment map prior to the wafer exposure. The use of this alignment algorithm during exposure using stepper technology also provides significantly better overlay capability by addressing defects such as mask run out, isotropic wafer scaling, rotation errors and orthogonality errors. Furthermore, this technique is well-suited to address the positional accuracy of the die after the compression molding process. This, in turn, will allow customers to utilize fan-out WLP technology for leading-edge design rules with smaller pad openings and tight overlay requirements.
It is anticipated that fan-out WLP will have considerable appeal for addressing the packaging requirements of the mobile phone market segment. The use of stepper technology will play a significant role in addressing the die positional tolerance concern while providing a cost- effective exposure solution. This manufacturing approach demands innovation and joint collaboration efforts within the entire manufacturing and equipment supply chain.
References
1. Gartner Dataquest Semiconductor Briefing, December 2008
2. M. Brunnbauer, et al, “An Embedded Device Technology Based on a Molded Reconfigured Wafer”, 2006 Electronic Components and Technology Conference
Manish Ranjan, director product marketing, may be contacted at Ultratech Inc, 3050 Zanker Road, San Jose, CA. 95124