By Paul Enquist and Chris Sanders, Ziptronix, Inc.
In 3D IC technology, thinned, planar circuits are stacked and interconnected using through silicon vias (TSVs). 3D vertical interconnect will be used for stacked, inter-chip connections and to repartition chip designs into smaller multiple layers that will form the required circuit. 3D ICs have the potential to alleviate scaling limitations, increase performance by reducing signal delays, and reduce cost.1 Enabling technologies for 3D IC include TSV formation, thinning, and alignment and bonding