(August 3, 2010) — In this video interview from SEMICON West 2010, Jan Vardaman, president/founder of TechSearch International, discusses 3D technologies in the real semiconductor engineering world. Especially for 300mm wafers, work is being done on processes and yield. She points to 2012 for widespread adoption of TSV. Vardaman speaks with senior technical editor Debra Vogler.

Vardaman also commented on copper pillar use for flip chip packaging, in the form of a Texas Instruments/Amkor product. Texas Instruments made a splash with partner Amkor, announcing qualification and production of a fine-pitch Cu pillar flip-chip package — <50μm, vs. ~150μm pitch size limitations with conventional solder-based flip chip, e.g. ball bond. The TI/Amkor announcement "represents one of the major adoptions outside of Intel and I believe it is the start of the wave," Jan Vardaman, TechSearch, told SST, in conversations during and after SEMICON West. (Read the article here: http://www.electroiq.com/index/display/packaging-article-display/4933608364/articles/advanced-packaging/packaging0/industry-news/2010/july/semicon-west_lesson.html)

Cu pillars offer advantages over conventional solder in terms of thermal performance, better conductivity, and resistance to electromigration, as well as shorter package routing (higher pin densities, reduced die sizes). TI executives explained the technology is ideal for applications ranging from ASSPs (smaller body size, high pin count, low-power aspects) to DSPs (same requirements), and power management (density more than pin count). Watch a video interview with Texas Instruments about the announcement here: http://www.electroiq.com/index/display/packaging-article-display/7346795089/articles/advanced-packaging/packaging0/wafer-level_packaging/2010/july/video_-wafer_level.html