Sesh Ramaswami, Applied Materials, Santa Clara, CA USA

Accelerated data exchange, reduced power consumption, and much higher input/output densities are all enabled by 3D integration using TSV technology. Memory makers will implement homogenous TSV integration to produce stacked DRAM to boost the memory capacity per unit board area / volume. This method reduces latency and increases bandwidth between the memory and processor. Applications for heterogeneous integration include image sensors or communication chips in mobile devices. TSVs can also be used to improve yield. Large die can be partitioned into functional blocks (resulting in smaller die with higher yield) and integrated vertically atop each other or adjacent to each other on an interposer.

TSV schemes

TSV integration can be implemented in a number of ways. The simplest form is that of a silicon interposer through which vias have been etched and filled with metal (typically copper). Such interposers also have multi-layer damascene interconnects which connect die placed adjacent to each other. Interposers enable end-product designers to quickly integrate two chips without making a TSV within the individual chip. Most of the development to date has focused on via-middle and via-last, wherein the TSVs are created within the active die. In the via-middle scheme, the TSVs are etched after contact/transistor formation but before back-end-of-line (BEOL) processing. Via-last TSVs are created from the back side of a thinned wafer, creates the vias after BEOL processing.

Technology development and commercialization

Since the onset of the TSV "buzz" in mid-2008, the scope and content of the development program has been guided by a methodical evaluation of many aspects, including end-product requirements, market timing, industry eco-system, cost-effective process sequence integration, and manufacturing-worthy unit processes. This framework also provided common goals for collaboration among adjacent technologies to accelerate industry learning. Implementation risk is being mitigated not only through these collaborations but through joint prototype testing of process flows. The three overriding objectives that guide the integration work are: wide process window, capability to withstand processing on fragile bonded/thinned wafers, and overall cost of ownership of the fabrication flow.

Figure 1. Etch technology demonstrates high resist selectivity, in situ dielectric open, combined with excellent profile control.

In the past year, considerable progress has been made in optimizing results for each of the unit processes involved (Figs. 1-5). In etch, optimization between etch rate, profile and related parameters are well understood, with excellent performance demonstrated on aspect ratios typically ranging from 4:1 to 12:1. A process for dielectric liner deposition has demonstrated >60% step coverage on aspect ratios up to 12:1. The capability for depositing in excess of 1µm of oxide on via sidewalls makes this a versatile film for a wide range of aspect ratios. Titanium or tantalum barriers and PVD copper seed layers have been co-optimized with electro-chemical deposition to ensure void-free metal fill. For via-last processes, thermal budget becomes a significant concern, since device wafers are processed while being temporarily bonded to carriers. Dielectric and PVD depositions have been refined to achieve desired mechanical and electrical film qualities and process performance at temperatures below 200°C.

Figure 2. The CVD-based dielectric is capable of depositing conformal liners in a wide thickness range and enables electrically robust dielectric insulation for interposers and high-aspect ratio TSVs.

Depending on the TSV processing sequence adopted, dielectrics (oxide, nitride) or metal (copper, barrier) must be removed using chemical-mechanical polishing (CMP). Recent work has enabled optimal bulk removal rates with the requisite process controls to accurately transition between layers and preserve surface topography. Other advances have also improved the cost-efficiency of this step, contributing to the goal of optimizing the overall cost of the manufacturing sequence.

Figure 3. Electrochemical deposition of copper can achieve a conformal lining and void-free fill for vias. A co-optimized etch, liner, and PVD barrier/seed ensure a broad fill process window.

The process steps outlined above (etch through CMP) have been developed primarily on production-proven 300mm platforms. Thus, the traditional risks associated with new equipment have been largely mitigated. Foundries and independent device manufacturers were able to start development work in 2008, with minimal new investment (hence, at low cost) by re-using existing equipment. Thus, it may be surmised that these processes can be ramped to pilot production as needed by the market, with full production capability later in 2011. Costs [inputs to the cost of ownership (CoO) model] are well understood in the industry, and CoO reduction roadmaps are easily comprehensible.

Figure 4. Rapid removal of copper layers with good surface topography and end points at copper/barrier and barrier/oxide interface; co-optimized with electrochemical deposition for low cost of ownership.

Figure 5. Redistribution layer relocates via locations. In TSV integration, it enables pads to be aligned between heterogeneous die. Shown is a copper redistribution line formed with PVD barrier/seed and electrochemical deposition, encased with low-temperature (<200°C) dielectric.

Bonding/debonding

The situation is different for temporary bonding and de-bonding of wafer carriers. While the learning from 200mm CMOS image sensors had been initially leveraged for preliminary 300mm silicon processing, several elements needed to be modified. Glass carriers are mandatory (for optical transparency) and remain in place as part of the image sensor end-product. Glass and silicon substrates have displayed the requisite mechanical handling repeatability. In high volume silicon processing for logic and memory (the focus of this article), carriers need to be re-used. Current lithography systems used in packaging fabs provide the alignment capability to look through silicon. Hence, glass carriers are not an absolute requirement. Silicon carriers are preferred as they are manufactured to industry- standard dimensional specifications, are less prone to breakage (and therefore easier to recycle), and can thermally and electrically couple with the wafer. In carrier management, the challenges are bonding tolerances, total thickness of the wafers and substrate, flatness of the substrate surface, thickness and thickness uniformity of the adhesive, adhesive coating, and processing and grinding. In the past two years, good progress has been made on developing appropriate adhesives, with second-generation bonding materials showing much improved results.

From a supply chain perspective, processed wafers need to be shipped between the TSV facility and outsourced assembly and testing, which can be done either as bonded wafers or on tape. For the former approach, bonding and de-bonding needs to be matched in terms of equipment set and put a constraint on the supply chain between the fab and the assembly house. Shipping on tape may be an acceptable option, but needs to be validated by the supply chain. It would behoove the industry to standardize on carriers, adhesives, and the associated processes of bonding and de-bonding so that these specific unit processes can be exercised in iron-man type testing and transitioned to cost-effective production. To drive this "standardization," the current collaborations between material and equipment suppliers and users need to be accelerated to release a commercial solution for temporary carrier management.

Conclusion

Today, unit processes are ready and integration is well advanced, with "best known methods" for typical interposer, via middle, and via last flows ready for limited pilot production at several locations. Products for TSV creation have been proven in the 300mm manufacturing environment and paths for process improvement and CoO reduction are well understood. Processes and products in wafer-level thinning and die-level processing are evolving rapidly.

For volume production, end-product value must be balanced against wafer cost. The end-product value will vary widely depending on application and hence the cost-threshold may vary. The total cost to achieve a device stack is split between wafer-level TSV creation (etch, dielectric liner, barrier/seed, ECD fill, and CMP), wafer-level thinning (bonding, thinning, and de-bonding) and die-level processing (dicing, stacking, assembly, and testing). Current costs of the latter two steps are in excess of 50% of the overall cost and industry standardization (or at least convergence) will help reduce the cost of materials and accelerate the release of higher throughput equipment.

Biography

Sesh Ramaswami is Sr. Director, Strategy in the Silicon Systems Group at Applied Materials; email  [email protected].

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