(July 30, 2010) — In this video interview, Craig Mitchell, Tessera, comments on 3D packaging and interconnect, speaking with senior technical editor Debra Vogler. The chip industry is using packaging technologies to address miniaturization and density. Materials are posing a challenge.

Mitchell sees copper taking a more important role with better cost and reliability. Flip chips are migrating to finer geometries, and low-k dielectrics are very fragile, prompting a change in interconnect and passivation technologies.

Mitchell also explains Tessera’s recent Cu development, wherein Tessera is working in copper application from substrate up to the die. This minimizes changes to the die side, making use of substrate technology instead.

See more packaging articles and news here: http://www.electroiq.com/index/packaging.html