May 31, 2011 – STATS ChipPAC says it has widened its range of packaging configurations for its fan-out wafer-level packaging technology. Integrating through-silicon via (TSV) with integrated passive devices (IPD), on the company’s embedded wafer-level ball grid array (eWLB) platform, addresses complex designs, shrinking lithography nodes, and increased performance demands for mobile and consumer applications, according to the company.

Interconnecting through the silicon wafer surface (instead of around via wires) better utilizes space efficiency, improves formfactor, and improves electrical performance. Use of TSVs is particularly beneficial with passive devices, which take up a lot of space (up to 60%-70%) in a subsystem or SiP package.

Integrating the eWLB, TSV, and IPD technologies, "opens up a wide range of possible design configurations for SiP and 3D packaging at the silicon level," said Han Byung Joon, EVP/CTO of STATS ChipPAC, in a statement. "This is an effective approach to system partitioning which offers our customers an overall better system performance."

The company’s expanded range of package architectures includes single die, multi-die, ultrathin, system-in-package (SiP) and 3D packaging, with what the company calls "superior electrical and thermal operating characteristics."

Learn more about STATS ChipPAC at www.statschippac.com

Georgia Tech researchers have promoted an "all-silicon" packaging concept for several years, calling for integration of wafer-level and 3D stacking technologies to bring tighter node silicon, vertical die integration, and embedded passives together. Read about the idea in 3D Technology and Beyond: 3D All Silicon System Module by Ritwik Chatterjee, Ph.D., and Rao R. Tummala, Ph.D, Packaging Research Center – Georgia Institute of Technology