December 27, 2011 — Small, mobile, Internet-connected devices are bucking the slow economy and use advanced packaging technologies to pack an enormous amount of functionality into a very small form factor, notes New Venture Research. The chip packaging method also determines the speed and performance of that chip, as well as its battery consumption.
Advanced IC packaging technologies include system in package (SiP), stacked packages, fan-in quad flat pack no leads (QFN), fan-out wafer-level packages (WLP), and interconnection styles of 3D and 2.5D through-silicon vias (TSV) and flip chip. The use of these packaging technologies for mobile electronic devices is covered in New Venture Research’s Advanced IC Packaging Technologies, Materials, and Markets, 2011 Edition.
Stacked packages are essentially a vertical multichip package. They come in many forms, including die stacks, package on package (PoP), package in package (PiP), TSOP stacks, QFNs, MCMs, and WLPs. Now found in all cell phones, stacked packages are in a high-demand market. Stacked package revenue will experience a 10% compound annual growth rate (CAGR) through 2015.
TSVs/3D interconnect creates a die stack with short interconnection distance for high speed, low power consumption, reduced parasitics, and small form factor. Vias go through the silicon, electrically connecting the die vertically. It replaces wire bonds and other second-level interconnects. The identified potential markets for TSVs will grow from 35 billion units in 2010 to over 54 billion in 2015.
System in package (SiP) devices are a functional block, a system of electronics that combines functional units together onto a single substrate to enable the shortest electrical distance between parts for superior performance. This reduces the amount of traces going into and out of the package, enabling a more simplistic PCB for the final product and potentially reducing system costs. Revenue for SiPs will expand at a 5.4% CAGR through 2015.
To increase the reach of the QFN package, fan-in QFN involves extending the number of rows of leads from the usual one to two or three rows. This allows hundreds of package leads, up from the 50 or fewer in a traditional package design. Although the number of fan-in QFNs assembled currently is quite small, the potential is huge, with a projected CAGR of 63.1% for revenue through 2015.
Reconfigured or fan-out wafer-level packages (FOWLP) were introduced in 2006. After devices are manufactured on a wafer, the devices are sawn and transferred on a carrier to another larger wafer that has gaps between die, which are filled with overmold material that also coats the back side of the devices for protection. This allows for a larger surface on which to extend a redistribution layer, thus allowing for far more I/Os than would be possible on the original smaller WLP surface. Solder balls or bumps can be added to this surface for interconnection to a printed circuit board (PCB). Fan-out WLPs are expected to have a CAGR of 15.9% for revenue through 2015.
Cellular handsets are the primary handheld electronic gadget globally, especially in areas too vast to support wired communication lines. Cellular handsets are growing at an 8.5% CAGR between 2011 and 2015, and smart phones, a subset of total cellular handsets, are growing at a 15.2% CAGR.
More information can be found on these topics and others in the new report, Advanced IC Packaging Technologies, Materials, and Markets, 2011 Edition, from New Venture Research at newventureresearch.com.
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