November 16, 2011 – A host of companies are offering, or are in development with, fan-out wafer-level packaging (FO-WLP) for devices with large numbers of I/Os as an alternative to going finer-pitch (0.3-0.35mm) to keep using conventional fan-in technology, says TechSearch International, in an updated report.

Fan-out WLP offers the same low-profile advantage as conventional WLP: singulated die are placed into a "reconstituted wafer" with enough space around each chip to accommodate second-level connections. Among those offering or prepping FO-WLP options is the newly launched Deca Technologies; TechSearch cites Deca president/Tim Olson praising the "tremendous" promise of the technology to improve cost, inflexibility, and cycle times for tooling substrates, assuming the industry can overcome some "capital disadvantages and a few engineering challenges. "We are close to a tipping point," he says. Others offering FO-WLP include the usual SATS firms (Amkor, ASE, SPIL, STATS ChipPAC) plus a host of others including ADL, Freescale, Fujikura, Intel (via Infineon’s wireless division), King Dragon, Nanium, Nepes (via Freescale’s 300mm RCP line), Renesas, and Teramikros (n