Version 2008 of Applied Wave Research’s (AWR) Analog Office design environment is targeted for radio frequency integrated circuit (RFIC) design, and reportedly includes numerous enhancements to the user interface and design flow for increased user flexibility and productivity. Project, elements, layout tabs, and the status window are now dockable and floatable, providing a design environment that is fully configurable to suit personal preferences. Useable screen space is maximized for handling of complex designs.

The APLAC harmonic balance engine is said to deliver better convergence on highly non-linear circuits, circuits with thousands of transistors, and circuits in which the transistors are driven deep into compression. Nonlinear noise analysis is now reportedly 100 times faster and consumes 90% less memory. Improved extraction flow enables simulation of interconnects using frequency-domain models in AWR’s ACETM technology in addition to more traditional RLCK extraction. For very-high-frequency designs, the same layout can be extracted to AXIEM, AWR’s 3D planar EM solver for increased accuracy. AWR’s Precision Design Rule Checking (DRC) engine user interface streamlines the look and feel of DRC capability whether the engine being used is AWR’s Precision, Mentor Graphics’ Calibre, or Cadence Design Systems’ Assura. Applied Wave Research, Inc, El Segundo, CA; www.awrcorp.com