October 27, 2011 — ACM Research Shanghai, Ltd., introduced the integrated Ultra iSFP stress-free polishing (SFP) semiconductor manufacturing tool for 65-45nm copper (Cu) interconnects, improving through silicon vias (TSV) with better heat dissipation. SFP’s electrochemical mechanism is combined with ultra low down force chemical mechanical planarization (ULCMP) and thermal flow etch (TFE) to avoid damaging the underlying device structure while boosting performance.

The Ultra iSFP LDCMP uses endpoint detection to ensure a continuous 150nm Cu film, protecting the underlying low-k structure. A brush clean removes large particles and a space-alternating phase shift (SAPS) megasonic clean removes tiny particles and oxide. An in-tool non-contact component measures Cu thickness. SFP then selectively removes the non-recess Cu to the barrier, followed by a bevel cleaning step. The wafer finally enters the TFE process where the barrier is removed after pre-heat, and the wafer is cooled. An equipment front end module (EFEM) brings the wafer to the front opening unified pod (FOUP).

The Ultra iSFP forms SiO2-based air gap interconnect structures with a traditional SiO2 dielectric and damascene process and an automatic alignment structure, with no hard mask required. SFP is able to control global Cu line recess and dishing by using a pre-measured Cu film thickness map. There is no erosion or deformation to the dielectric layer and barrier during SFP. Air-gap interconnect structures are selectively formed in narrow line spaces for reportedly better heat dissipation and mechanical strength. Air gap interconnect structures can be fabricated with copper line-widths of less than 0.2