Second-level reliability characterization using temperature cycling
by HDP USER GROUP
International Inc.
This article describes the investigation of the effects of temperature cycling upon solder joint connections at the board level for a variety of chip scale packages (CSPs). Variables studied were package construction, package location on the circuit board, solder joint location on the package, and printed circuit board type.
Temperature cycle evaluations were conducted with real-time event monitoring, and failed sites were subjected to failure analysis to determine cause of failure. These analyses were conducted by failure analysis teams at Hewlett-Packard, Lucent Technologies and Nortel Networks as part of a CSP reliability characterization project of HDP User Group International Inc. The group is an organization of semiconductor, materials and systems integrators who are concerned with the availability and reliability of semiconductor packages for high-density and high-reliability applications. One of the first projects undertaken under the auspices of the HDP User Group International Inc. was a ball grid array (BGA) reliability characterization project. The goal of that project was to characterize the package-to-board solder joint reliability with respect to thermal cycling with BGA devices; the CSP reliability characterization project, using CSP devices, was designed to use as many of the same parameters of the BGA project to allow direct comparisons of the results.
The Challenge of High-density
One of the most promising solutions for high-density applications is a new family of components called chip scale devices. Chip scale devices are, by definition, packages that require a board area of less than 120 percent of the area of the included die. While these packages are promising with respect to packaging density, their package-to-board solder joint reliability has been suspect. (This reliability category is also known as “second level” and will be referred to as such throughout the rest of this article.)
 Table 1. Test devices. |
This questionable reliability stems from two factors. The coefficient of thermal expansion (CTE) of the package is controlled primarily by the die itself, which tends to yield a CTE that is significantly lower than that of the printed circuit board (PCB) material. Also, the typical diameter of the solder balls that serve as the main stress relief is much smaller that what has previously been accepted.
The Analysis
Test Devices: Table 1 shows the devices used for the reliability test. To avoid conclusions before completing all testing and analysis, vendor names were not included. All of the devices analyzed have internal daisy chains on the die, with the exception of Device G, which is a micro-BGA that uses routing on the polyamide carrier. The test board included other devices that were not used because of the inability to get test devices in time to assemble the boards. Device A, a pitch ball grid array, and Device B, a type 1 TSOP, were included as control devices and are identified by an asterisk in Table 1.
 Figure 1. Test board (courtesy of Paul Collander, Nokia). |
The Test Board: The test board had four of each test device, which was designed as a single group and repeated four times (with the exception of the connector) so the layout was identical and all devices were evenly distributed across the PWB (Figure 1). The connector was a 37-position receptacle, right-angle DSUB connector. It was not populated to eliminate the added failure side and all wiring to the event detectors was directly soldered to the connector holes. Connectors were laid side-by-side; to fit four connectors in this configuration on the 11.2-in edge, the part outlines were placed end-to-end. One tenth of an inch was left on each end of the board to place the PWBs in a rack; placement was the same for each stackup version.
Connections: Each grouping was designed to “feed” one connector. All components in each component group were daisy-chained identically and connected to the same pin numbers on its associated connector. Each device had one daisy chain except as specified for the devices where two daisy chains were desired. Pin 37 on each connector was ground. Daisy-chain connections started at Pin 1 on the connector and each net connected to a subsequent pin until all nets were connected.
 Figure 2. Thermal cycling results for device C (outer). |
All remaining pins on the connector were connected to ground. (For example, of 32 total nets per group, pins 33 through 37 are grounded.). On devices where multiple nets were not used, a “shorting bar” was added outside of the device outline on the surface layers of the PCB, which allowed for separation (by cutting the trace) of sections of the devices (corners, “rings,” etc.) to aid in failure analysis after thermal cycling.
Test Details
This project used the standard HDP User Group temperature cycling test procedure. Each cycle lasted 40 minutes. Both rise and dwell times were 10 minutes. The temperature was cycled between 0 and 100° C, as measured at the top surface of the packages.
During temperature cycling, the nets of the samples were monitored for evidence of intermittent operation. This was done by plugging the harnessed samples into an event detector that is capable of sensing increases in resistance of 100 ohms for periods of time greater than 200 nanoseconds. These increases in resistance (or events) were considered failures and flagged based on time, cycle number and temperature. The nets of the samples were measured for electrical resistance every 20 seconds. The test vehicle was made up of three groups of ten of each PCB type. Because some of the devices had more than one test circuit, the final number of test nets was approximately 2,100.
 Figure 3. Voids on microvia boards. |
Before testing temperature cycling, cable leads were hand-soldered to the board contacts for use in real-time resistance measurements during temperature cycling. The nets were then all measured for baseline resistance. Next, the boards were temperature mapped. Temperature mapping was completed by putting thermocouples on the samples and placing the samples in the actual temperature cycling chamber. This ensured that all of the devices received the same input temperature stimulus during temperature cycle testing.
The thermal cycling was performed by Hewlett-Packard at its Palo Alto site. Temperature cycling consisted of subjecting the harnessed and monitored samples to 6,600 cycles of temperature cycling.
Failure Mode Analysis
The failure mode analysis (FMA) was performed by reliability laboratories at Hewlett-Packard, Lucent Technologies and Nortel Networks. The boards were sectioned and divided among the three laboratories equally. To obtain comparable results, the laboratories used the same microsectioning and photomicrography techniques.
Table 2 shows a summary of the Weibull Plot Distribution for the devices that completed the failure analysis test. The two-parameter Weibull characteristic life or the cycle for 63.2 percent failure and the two-parameter Weibull slope T are shown for PWB Types RCC, FR-4, SLC. See Figure 2 for the Weibull Plot for Device C (outer).
 Table 2. Thermal cycling results. |
One of the test devices (Device J) had excessive, initial open circuits so the sample size was too small for reliable data. Therefore, these device samples, which were not initially open, were not analyzed nor will their test results be given here. Four other devices, (Devices B, F, G, and H) did not have enough failures to merit having failure analysis performed. However, these overall results are given.
Conclusions
This project successfully investigated the solder joint reliability characteristics of several different types of CSP Devices mounted on printed wiring boards (PWBs). The variables studied were different circuit board materials (FR4 and microvia), different PWB design rules (for example, via in pad for microvia boards), CSP component location on the printed wiring board, the solder joint location on the CSP package, and the package construction.
The FR4 and microvia boards showed nearly equivalent performance in spite of the presence of voids in many solder joints on the microvia boards with via in pad. These voids appear to have been started by the microvia.
In failure analysis, there was no evidence of these voids influencing the failure modes (Figure 3), which are predominantly at the component attachment to SMT solder joint. The results indicate that this technology (including the evaluated variables) when applied in a product, should achieve reliable PWB assemblies at a reasonable cost. Since the completion of this project, the HDP User Group has extending this second-level solder joint reliability testing to include flip chip and wafer scale CSP devices. It has also started a similar effort in reliability characterization projects using lead-free solders with various board finishes.
Acknowledgements
The project team was comprised of the following individuals: Howard Allen (Fairchild Semiconductor), Carlos Avila (Hewlett-Packard), Paul Collander (Nokia Research), Theo Ejim (Lucent Technology), Don Foster (Amkor), Nikhil Kelkar (National Semiconductor), David Love (Sun Microsystems), Kevin Lyne (Texas Instruments), Irv Memis (IBM), Jeff Reibling (Hewlett-Packard), Lonnie D. Spurlin, project leader (Nortel Networks), Joe Smetana (Alcatel), Ahmer Syed (Amkor), David Towne (Sun Microsystems) and Viswanath Valluri (AMD).
BOB SULLIVAN is director of operations and RUBEN BERGMAN is executive director, European office, of HDP User Group International Inc. For more information, contact Bob Sullivan at 10229 North Scottsdale Road, Suite B, Scottsdale, AZ 85253; 480-951-7151; E-Mail: [email protected] or Ruben Bergman at Langbrodalsvagen 73, S-12557 Alvsjo, Sweden; 46 8 86 9868; E-Mail: [email protected].