 Palomar's gold bumping tool creates interconnection at the wafer level. |
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Wafer-level packaging (WLP) has been in place for a number of years, but only recently has it emerged as a serious option for mainstream packaging needs. (Figure 1 shows some representative WLP structures.) Most key packaging companies are involved in it in some way, and the input from various industry experts illuminates the current status and future trends.
WLP processing
Handling and test. One of the first places where WLP has emerged is in wafer probing. Test is a process that does not always fit neatly into either the front or backend of the process flow, so perhaps it is not a surprise that this is an area where the convergence is quite visible these days.
 Figure 1. Three variations on wafer-level CSP structures showing Fujitsu's “Super CSP.” (Courtesy of Fujitsu) |
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Electroglas, a supplier of wafer probers and yield management tools, made an important step in WLP. The company modified wafer probers to accommodate interconnects such as solder balls that are larger than typical die bond pads, thus creating WLP testers based on production equipment. Since then, the company has devised methods for handling singulated WLP wafers (Fig. 2).
 Figure 2. Handler for WLP processes. (Courtesy of Electroglas) |
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According to Tim Boyle, VP and CTO at Electroglas, “We're able to do this by processing material post-dicing while mounted on standard dicing frames. Currently we're in our second generation of WLP handler, which can accommodate — through proprietary alignment methodologies — the typical variation in package placement due to linear and nonlinear movement of the dicing film. For quality reasons, many WLP manufacturers insist that test be the final step in their manufacturing process.”
Material handling also was cited as a key capability for WLP technology proliferation by Kevin Crofton, VP and general manager of Newport Corp.'s Advanced Packaging and Automation Systems Division. Crofton said, “Advanced material-handling procedures, including speed, precision, and capacity, directly impacting yield, will be the determining factors in the growth of this technology. Advanced material handing, for example, allows automatic loading of wafers to and from cassette during processing, for greater efficiency.”
BTU, a thermal processing systems manufacturer, also sees material handling as an important capability. Tim Gillis, director of marketing, pointed out that in WLP processing, the value of the wafer is very high because it already has gone through all the frontend wafer processes. This makes the throughput and yield particularly important for WLP.
Gillis said, “Cost of ownership analyses are very common in frontend wafer processing. The analysis for WLP will be similar to frontend, except that the value of the wafer has increased greatly when compared to many frontend process steps. This will result in an increased emphasis on the cost of scrap, which will drive companies to increase yield and minimize wafer breakage. Reducing wafer breakage will require robust automation solutions for WLP. Increased atmosphere purity and thermal uniformity will be required to increase yield in wafer bump reflow.”
Datacon is another equipment maker with a focus on handling. In comments from David Halk, GM of Datacon North America, handling was again emphasized. “Datacon currently offers wafer-handling capabilities on our standard assembly module transport system,” noted Halk. “To address the specific needs of WLP, Datacon also is developing a robotic wafer handler that can be easily added to our existing machine platform. The wafer handler will deliver unmounted bare wafers to the assembly system to handle WLP applications.”
Underfill. One developing area as packaging processes shift to the wafer level is application of underfill to a wafer rather than to singulated flip chip devices that already are mounted on a substrate.
Asymtek, an underfill equipment supplier, is working with material suppliers and university consortia to find methods of applying wafer-level underfill. According to Steve Adamson, semiconductor packaging and assembly product manager, “This work is still in the exploratory stage, but the use of jetting technology to dispense around the solder balls on a wafer looks promising.” Adamson also sees the new jetting techniques providing advantages in limited accessibility applications, such as stacked die.
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Wafer-level underfill is also one area where March Plasma Systems is finding applications for its plasma technology. Plasma treatment systems (Fig. 3) have been used for many years for surface activation, contamination removal, etching, and cross linking. James Getty, applications and business development manager, noted that these functions are a good match for underfill processes. “Plasma increases surface energy that promotes underfill adhesion and capillary flow wicking speed,” Getty said. “It also shortens flow-out time and improves material flow uniformity for no-flow underfill materials. Enhanced fillet heights after plasma treatment improve the reliability of the package.”
Wafer bumping. Wafer bumping is another process area where plasma treatment is useful. Getty said of March Plasma's applications, “We have customers using our plasma systems to remove organic residue and oxides prior to the bumping process. Plasma also is used to roughen the wafer surface to improve adhesion prior to the BCB passivation layer process.”
In the deposition area of wafer bumping for WLP, there are many approaches and subtleties that experts in the field have identified. Valery Felmetsger of Sputtered Films, a supplier of deposition equipment, reported on stress control in thin films, which is important because stress can cause low adhesion and even delamination. There also can be problems with thin wafers, which can be warped by the stress in deposited films. Felmetsger found several factors that can help the thick nickel-vanadium films that are common components of under bump metallization (UBM). A low wafer temperature, radio frequency (RF) substrate bias optimization, and the use of a multistep process with pauses improve stress control.
Another deposition equipment supplier, NEXX Systems, sees a “real need for a company that builds processing equipment targeted at flip chip packaging,” said Michael Gustafson, director of sales and service. The expense of typical frontend equipment is prohibitive for the cost model of backend processing, according to Gustafson. NEXX Systems provides thick- and thin-film deposition sputtering equipment, as well as systems for metal and photoresist electrodeposition.
A different approach to WLP deposition is represented by Optomec's mesoscale writing technology. The technology is based on flow guidance and laser-assisted decomposition to provide lines down to the range of <10µm. The technology, dubbed maskless mesoscale materials deposition (M3D), avoids the use of masks and resists, and it writes lines onto polymer, glass, ceramic substrates or many other low-temperature substrates. According to CEO David Ramahi, the technology's applications include reducing bond pad diameter and pitch, as well as bond pad redistribution (Fig. 4).
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Another laser-based process with a place in WLP is laser drilling of microvias. NanoVia recently introduced a platform for drilling microvias, and, according to Todd Lizotte, VP of R&D, the system's ability to drill through silicon or spun-on dielectric films makes it a useful WLP tool.
WLP reliability
As always, reliability is a concern for any kind of new packaging technology. One important concern is the stress created in WLP structures, and one way to address this is to integrate low-modulus polymeric materials into the wafer fabrication process. Dow Corning, for example, provides silicone materials for this application. According to Mike Kunstleman, global market team leader, microelectronics packaging, “Unfortunately, many of the materials currently used in IC packaging (such as epoxies and polyimides) do not offer the flexibility to absorb stress at the wafer level. In contrast, new silicone formulations designed for wafer-level applications offer a modulus an entire order of magnitude lower than alternative materials.”
The ability to test the strength of WLP also is an important part of the equation. In this field, Instron, an equipment provider that tests mechanical properties, recently introduced a tool that does peel tests of thin films and substrates with such applications in mind.
Chip/package co-design: Manufacturability is the key
The concept of chip/package “co-design” has been discussed for many years, and most people are familiar with the potential advantages — better system partitioning, testability, electrical performance, miniaturization, and so forth. In reply to our question, “How do you see chip designers and packaging designers working together?” much of the input focused on manufacturability.
For example, Crofton of Newport Corp. told us, “Chip and package designers must work together to achieve the desired goals, and in particular to work together on design for manufacturability issues.” Crofton sees applications as a driving force: “Increasing levels of miniaturization driven by new and more powerful consumer electronics products present a constant challenge to chip and package designers since next-generation packages will present issues that must be addressed, including lower cost, finer pitch, and improved board-level reliability.”
With manufacturability being a key issue, the equipment suppliers must be in the loop, according to Halk of Datacon. “Sometimes we see chip and package designers working together and also talking to backend equipment manufacturers. If they design products with backend assembly in mind, they will end up with a faster, higher-yield product with a shorter time to market. Talking to equipment manufacturers enables designers to produce their products using standard equipment,” said Halk. “The most successful companies will use this strategy to stay ahead of the curve.”
Some of the manufacturability issues are subtler than the obvious need to include all parties involved in the manufacturing flow. C. J. Berry, Amkor Technology's director of advanced packaging wafer processes, expressed an interesting thought about counterintuitive benefits of increasing the die size for the sake of a less expensive chip/package combination. Berry said, “It is heresy to suggest that a fab manager consider jeopardizing the 'good die out' horizon by sacrificing die shrink, or, heaven forbid, even growing a die. In certain cases, however, die shrink (or design) is known to drive up the final packaged part cost by dollars (more than several) due to the substrate technology it drives.”
“In certain cases,” continued Berry, “it can be proven that slightly increased die size results in lower overall package cost (even including the die cost increase for this). Design decisions similar to this are made every day that potentially affect a 'downstream' technology requirement that may be more expensive than otherwise required if the system is designed as a whole.”
While manufacturability currently is prominent as a key driver for chip/package co-design, performance was the original motivation for it. Bruce Hueners, VP of marketing at Palomar Technologies, summed it up well: “Flip chip attachment to package and embedded passives on the package will be key enabling technologies to package-level performance. Increasing demand for chip function is stressing the chip and packaging interconnect requirements. It is evident that packaging design trade-offs no longer can be made independently of the chip and system.”
As Hueners pointed out, one of the clearest and most important areas in which chip and package designers need to interact is in flip chip design. Gregory Phipps of Advanced Interconnect Technologies discussed the need for communication in “Teamwork: The key to success in flip chip design” (p. S4). Mark DiOrio of MTBSolutions also had some thoughts on the importance of design. See his comments on maximizing performance in “Silicon to package integration — breaking the packaging bottleneck” (p. S5). The equipment and materials suppliers must, of course, be involved and Jack Belani of Kulicke & Soffa provided that perspective in “Cost and performance will drive convergence” (p. S8).
Finally, perhaps the most meaningful viewpoint is found at a chipmaker. Tom Murchie of Altera related the importance of package design in “Packaging's role in product development.” (see above) Murchie confirmed that “there is a greater need for integration and comprehension of the interactions among wafer, package, and printed circuit board (PCB) technologies in new product development.” He also told us some good news: “We see significantly increased interactions between silicon and package engineers.”
Jeffrey C. Demmin, editor in Chief, advanced packaging
Teamwork: The key to success in flip chip design
The flip chip design process currently operates where IC and PCB designers, as well as backend subcontractors, work relatively independently on wire bond designs. Typically wire bond designs do not have the performance requirements of flip chip designs. Thus, the routing requirements and design constraints are fewer. Additionally, as I/O counts are lower, the die pad arrangement, wire bond layout, bond finger placement and route pattern are determined by the wire bond assembly rules; therefore, the wire bond design process is much more straightforward.
With flip chip, designers of ICs and PCBs and subcontractors, must collaborate very closely on a design solution suitable for all three parties. The design process must be focused on the system level, and involve both the IC functionality and the PCB routing characteristics and rules. The chip designer must design IC functionality properly but also must be knowledgeable in substrate design and layout so that the design concepts work in terms of signal integrity and routablity on the substrate level. This means that the subcontractor and IC designer must work closely to develop a bump pattern that conforms to the design rules and routing required on a substrate.
Collaboration is also important to ensure an efficient design cycle. Flip chip packages require hands-on design work, as design automation is limited in the tools currently available. Also, there are many more considerations involved — design parameters, customer modifications, and modeling — that impact cycle time. Given these factors, manufacturers and subcontractors must ensure continuous communication and teamwork to optimize time-to-market.
Additionally, software vendors are developing new tools to facilitate IC/package co-design. The goal is to provide a single environment that can manipulate the I/O plan at both the chip and package level. Design activities, such as reading and writing both chip and package data, will occur in the same design tool environment, greatly improving the collaborative effort.
Today, IC manufacturers are looking to backend subcontractors to provide integrated services ranging from design to assembly to test. Chipmakers want them to be their total manufacturing solution provider and key member of their team. Subcontractors are offering these services and collaborating with IC manufacturers to streamline the assembly and test process, shorten lead-time, reduce time-to-market, and enhance operational efficiencies.
Gregory Phipps, design manager, Advanced Interconnect Technologies Inc.
Silicon to package integration — breaking the packaging bottleneck
Until recently, we kept semiconductor technology disciplines at arm's length. That is, silicon device technology was kept almost completely separate from packaging technology. With the advent of increased functionality demands and signal speeds in the RF realm, we can no longer partition these technologies if we are to achieve higher degrees of component performance. Packaging's role is no longer just to be a silicon carrier, but an enabler of the device's electrical performance.
To achieve increased performance, the silicon and the package must become one, integrated so that the wiring layers and interconnections of the silicon chip and the package are indiscernible. To accomplish this, the chip and packaging designers must work together closely. Each must understand not only the design rules of the other, but also the electrical performance values achievable with an integrated design. Today's package designer must be as capable of electrical design structures and skill sets as his counterpart in silicon.
 The interconnect structures of the MTBSolutions' packaging technology include a low-k dielectric material and copper. |
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At MTBSolutions, we recognize the need to enhance component performance by breaking the packaging bottleneck. Our high-speed and RF package design and cell libraries are every bit as complicated and as detailed as what you would expect to find in the silicon side (see figure). RF package design is a mixture of safety-first considerations, such as signal path length and matched routing for all differential pairs. Antenna functions are critical to system performance. This typically involves moving I/Os in controlled impedance waveguide structures.
The inability to mix input RF and output RF lines across die backside multizone power and ground planes, however, forces us to have component sizes greater than die sizes by a margin allowing for routing and power/ground management. This, in itself, departs from conventional WLP or chip-scale packaging (CSP) techniques that are aimed at smaller form factors.
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Mark diOrio, ceo, mtbsolutions inc.
Cost and performance will drive convergence
In today's marketplace, the majority of chip and package designers are not working together. A “throw it over the wall” mentality persists.
While there has been some progress to bridge that gap, the industry is nowhere near where it is supposed to be. A few of the larger integrated device manufacturers have done a reasonable job merging wafer and chip design activities. Some systems companies also have made progress in that regard. However, the merchant semiconductor companies still have much work to do.
Additionally, the tools provided by suppliers, such as wafer probe cards, bonders, encapsulants, and package test sockets, have not been integrated effectively into the design process. Rather than first designing a chip and a package, and then finding a way to assemble it, manufacturers need to design solutions that include all the appropriate tool sets. Probe card and socket design needs to be completed at the same time as chip and package design so that wafers and packages can be tested — everything must work together.
Going forward, the next 5–10 years will mark the era of convergence in the design space. Tool suppliers will play a significant role in that activity. The need to optimize cost and performance will drive this transition. Is it better to place the interconnect on the chip or package? What are the cost-performance trade-offs of one approach vs. the other? Designing for optimum manufacturability and yield will also be more critical than ever.
Design globalization is another thing that needs to happen. Backend assembly takes place primarily in Asia, while frontend fabrication is skewed toward the United States, Europe, Taiwan (and China in the next few years). This model is not going to disappear overnight. There is a need for better information exchange between designers and suppliers, along with around-the-clock design capabilities.
As chip performance increases in terms of integration and/or speed, the rest of the electronic system is increasingly stressed, potentially limiting system performance. Combining and optimizing design at the system level will result in the best possible performance/cost combination.
The “throw it over the wall” era must end. Chip, package, and tool designers must work more closely together as we continue down the curve of Moore's Law.
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Jack Belani, vp, marketing, Kulicke & Soffa
Packaging's role in product development
As a programmable silicon solutions provider, we have recognized packaging as a key enabler for our products. Over the last three years, we have integrated our product planning and silicon engineering efforts with package design and development to ensure that we have delivered the most cost- and performance-effective solutions to our customers.
As we drive increased performance in terms of higher clock speeds and thermal needs, there is a greater need for interaction integration and comprehension among wafer, package, and PCB technologies in new product development. This requires the packaging side of the equation to provide information similar to what the wafer foundries provide — accurate performance and cost models — to product-planning teams to enable effective trade-off analysis between silicon and package design.
The associated technology development efforts have to be initiated significantly ahead of product to enable readiness at the time of product launch. Consequently, we see significantly increased interactions between silicon and package engineers, necessitating development of tools and methodologies that facilitate this integration. At Altera, we are pursuing this direction as well as looking into enabling solutions such as WLP and system-in-package solutions for our next-generation products.
Tom Murchie, VP of operations, Altera Corp.