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Packaging almost seems like the kind of enterprise that has to have a finite future. Think about it – our task is to package chips while adding as little as possible to the size, cost and parasitics that detract from performance. This means that there is a limit on everything. Once you get to zero additional size, cost or parasitics added, there is nothing else to do. Even if you haven't quite reached “zero,” the cost of pushing closer might not be worth it.
We are actually close to the endgame if you believe that view of packaging. We have chip-size packages that add nothing to the size of the device. It would seem impossible to improve on that. In the cost realm, we are constantly driving cost down the asymptotic slope. As for performance, the miniscule conductors in many packages these days add picohenries rather than nanohenries to the inductance.
I propose here, though, that it is time to take packaging past that “zero barrier” and actually have a positive effect on the device, rather than simply as small a negative effect as possible. How? The technology exists now to allow the packaging scheme to improve the performance and decrease the cost of semiconductor devices. The catch is that the chip and the package must be designed together.
There have been calls for “co-design” many times over the years, but it is a tough sell to get a chip designer to sit down with a package designer at the beginning of the design phase. This is the only way that it can work, though. By rearranging chip layout so that, for example, some of the interconnect can be taken off of the chip onto a substrate in a package, the performance can be improved. In some cases, the fancy packaging scheme can even decrease the overall cost by increasing the yield of the chips, if the packaging has taken on some of the wiring layers normally found on the chip. The technology exists, but the right mindset to take advantage of it is still in the wings.
It should be our industry's job to spread the word about this and fight the battles to create a real and comprehensive link between package design and chip design. If we don't, there will be no more room for package development ellipse and no demand for people to work on it! AP
Thanks for reading,
Jeffrey C. Demmin
Editor-in-Chief
[email protected]