Board-level Reliability and Testing
BY CHAOWEN CHUNG, ZAFER KUTLU AND SARATHY RAJAGOPALAN
Flip chip packaging has seen explosive growth in recent years, with more and more high-performance devices being designed in flip chip technology. Additionally, flip-chip-in-package (FCIP) is increasingly seen as a solution for higher I/O devices.
LSI Logic has developed an assembly process for organic flip chip packages, and a cross-section view of a flip chip plastic ball grid array (FPBGA) package is shown in Figure 1. It consists of a die flipped and attached to an organic substrate using eutectic solder bumps. The solder bumps on the die are either in a full array or in a depopulated grid array. An underfill epoxy fills the gap between the die and the substrate to provide a reliable connection between the die and the organic substrate. The package has a stiffener ring attached directly to the substrate to reduce the warpage due to the mismatch of the coefficients of thermal expansion (CTE) of the die and the substrate. A heat spreader is attached to the top of the die with a thermal compound and to the stiffener to provide a thermal path for enhanced heat dissipation.
Organic laminate-based substrates are based on high-density build-up and laser-via substrate manufacturing technologies. Organic flip chip packages have low-resistance copper interconnects and low-dielectric constants. The CTE of organic substrates is closer to the CTE of printed circuit boards (PCB) than the CTE of ceramic substrates. This reduced CTE mismatch between the substrate and the PCB enhances the reliability of solder joint interconnects.
Why Board-level Study?
Flip chip packages with ceramic substrates have been used for several years. The industry has generated a significant amount of board-level solder joint reliability data for ceramic packages. During the last few years, the electronics industry has been generating board-level reliability data on organic flip chip packages.
In the past, board-level studies were carried out by OEMs. Due to the increasing trend in board assembly outsourcing, this task has been transferred to the component suppliers as well as electronics manufacturing services (EMS) companies. As a result, LSI Logic established a board-level reliability program and has been generating data to provide a total solution to customers, which includes package- and board-level qualification. The board-level reliability testing is guided by the IPC-9701 specification “Performance Test Methods and Qualification Requirements for Surface Mount Solder Attachments.”
Reliability Assessment
Various FPBGA packages have been subjected to board-level evaluations. Table 1 details two build-up FPBGA packages that represent organic flip chip packages offered by LSI Logic.
 Figure 1. A cross-section showing the structure of a flip chip plastic BGA. |
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The key parameters and conditions that have been used are summarized below:
- PCB thickness: 0.062 and 0.093″
- Number of Cu layers: 8 and 12
- PCB pad: Non-solder mask defined (NSMD)
- PCB pad surface finish: Organic solderability preserve (OSP) and selective solder strip (SSS)
- Design: daisy chain die
- Electrical monitor: in-situ monitoring via event detector or data logger
- Test condition/duration: 0 to 100°C/6,000 cycles
- Process condition: primary reflow and rework.
An example of a Weibull plot reflecting solder joint fatigue for 45 and 40 mm FPBGAs using a 0.09″ thick PCB is shown in Figure 2. At the outset, the data shows that the solder joint reliability exceeds 4,500 cycles for 40 and 45 mm FPBGA packages.
 Figure 2. A Weibull plot of 45 and 40 mm flip chip plastic BGAs with a 0.093″ thick PCB. |
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Manufacturability Assessment
In addition to board-level reliability, the results obtained from LSI Logic's board-level manufacturability studies and from field reports from various users demonstrate that 1.00 mm pitch FPBGA packages are very robust from the board assembly point of view. Conventional surface mount equipment and processes can be used for these packages without any concerns.
Solder paste deposition. The most important contribution that the solder paste makes towards yield is to provide the flux to facilitate good pad wetting. Using too much solder results in little improvement in solder joint standoff, while the probability of solder bridging increases dramatically. Either 0.005 or 0.006″ stencil thickness with an aperture opening of 0.018 to 0.020″ is a good range to work with. The final decision of stencil design also should consider PCB and component factors.
Reflow soldering. The organic flip chip package allows the use of 63Sn/37Pb eutectic solder balls as the interconnect between the package and PCB. This is in contrast to the high-lead solder columns often used with ceramic substrates.
To obtain the temperature distribution across the entire PCB, thermocouples were used (Figure 3) to obtain the reflow profile at the following locations:
- PCB
- Highest thermal mass package, such as FPBGA, at both the package body and the solder joint
- Lowest thermal mass package
- Densely populated area.
The reflow parameters outlined below are the guidelines for reflow soldering of FPBGA packages:
- Preheat ramp rate: ≤ 4°C/second
- Time between 130°and 183°C: 90 ±30 seconds
- Solder joint peak temperature: 210° ±5°C
- Solder joint dwell time above liquidus temperature: 60 +40/-15 seconds.
- Package body/heat spreader peak temperature: ≤ 225°C .
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The in-circuit test (ICT) and reliability results obtained were excellent given the solder paste selected (no-clean), board pad surface finishes used (OSP and SSS) and packages (40 x 40 and 45 x 45 mm body sizes) using the reflow parameters listed above.
Rework. Special attention is needed for FPBGA rework, especially the reflow profile. Due to the localized heating process of a rework station and the heat spreader package construction, a greater temperature differential between package body and solder joint could be observed. Consequently, the package body could become overheated (>225°C). Therefore, it is important that the temperature of the package body, i.e., the heat spreader, is being measured with the solder joint temperature during the profile development.
 Figure 3. Thermocouples were used at various locations to measure the temperature distribution across the PCB. |
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The key is to use underboard heating as well as component preheating to minimize the temperature differential. The following parameters were used for board-level reliability testing.
- Underboard preheat: 80° to 100°C
- Component preheat: 90 to 120 seconds between 130° and 183°C.
- Solder joint peak temperature: 205° to 210°C
- Solder joint dwell time above 183°C: 60 to 100 seconds
- Package body peak temperature: ≤ 225°C.
Conclusion
Board-level reliability and manufacturability data was generated for various organic flip chip packages. The testing and other processing described provide guidelines for further evaluations, and the data shows positive results for the reliability and manufacturability of organic flip chip packages.
Chaowen Chung, Ph.D., Zafer Kutlu, Ph.D., and Sarathy Rajagopalan may be contacted at LSI Logic Corp., 1551 McCarthy Blvd., Milpitas, CA 95035; (408) 433-8000; Fax: (408) 433-7725; E-mail: [email protected]; [email protected]; and [email protected].