SHANGHAI, China – Verisilicon Holdings Co., Ltd., an ASIC design foundry, semiconductor library, and intellectual property (IP) provider, along with Semiconductor Manufacturing International Corporation (SMIC), will release a standard design platform (SDP) for 0.13-μm low-leakage processes. SMIC also partnered with Cadence Design Systems to create a low-power digital reference flow to address IC designers needs in the computing, consumer, networking, and wireless markets.

The SDP will include memory compilers for single- and dual-port SRAM, diffusion-programmable ROM, two-port registers, and standard and I/O cells. It was optimized for low-leakage and low-power, and was proofed in silicon via SMIC’s 0.13-μm, low-leakage silicon shuttle prototyping. Targeting significant reductions in IC power consumption in battery-powered applications, the platform will support EDA tools from Cadence, Synopsys, Magma, and Mentor Graphics.

The SMIC-Cadence reference flow will support SMIC’s advanced 90-nm system-on-chip (SoC) process technology. Incorporating a digital IC design platform and design-for-manufacture (DFM) technology, the platform will resolve low-power, complex-hierarchy, timing, and signal integrity (SI) sign-off issues associated with nanotechnology designs. Cadence used SMIC process technology and sample designs when developing the product. It comprises complete RTL-to-GDSII flow, including logic synthesis, simulation, design for test, prototyping, and more.