BY KEITH FELTON
oday’s designers continually strive to pack more functionality into smaller component footprints, and provide more end-customer value by reducing the effort and the risk inherent in designing new devices and technology. An approach gaining popularity, especially where small form factor and low power is concerned, is multi-die packaging.
The most common style of multi-die packaging is stacking, usually memory on top of an ASIC or some type of processor. To put some perspective on this, most stacks today are just 2 to 3 die. The base die is either flip chip attach or wirebond attach, while the stacked die are nearly always wirebond attached. The stacked die are either bonded directly to the substrate or down to their host site. With only 2 to 3 die to assemble, the number of stacking permutations is low. This lowers the number of concepts to be explored, making the task complexity fairly simple. With more than 2 to 3 die to assemble, the concept exploration phase becomes more important in the effort to achieve the correct stack configuration and meet design goals and parameters.
Today, the industry is rapidly marching well beyond the 2 to 3 die paradigm. An example is a major Japanese company’s recent announcement that it had completed a mainstream design containing an 8-die stack. Obviously, coming up with the final configuration and implementation of such vertically challenged designs was complex and time consuming. The challenges, however, do not stop at mechanical stacking. They become even tougher, as direct die-to-die attachment (using a common RDL layer to make the connections) is used. This method is becoming increasingly popular, especially for memory mounted on ASICs and processors.
With this level of die assembly complexity, the designer or project architect is faced with the exploration of multiple design concepts to find a solution that meets electrical performance, cost, yield, thermal, power, and above all else, manufacturability needs. The challenge here is to explore and select a concept in a reasonable timeframe – usually never short enough to meet marketing’s time-to-market goals – so that that the concept can be implemented and the package fabricated and assembled.
An immediately noticeable challenge is that virtually all the EDA tools for fabric physical layout (IC, IC package, or PCB) are 2-D. Design is done in a 2-D, plan view process. While ideal for substrate layout, interconnect planning, metal fill creation, etc., this approach does not lend itself well to the design, management, and verification of complex die stack towers.
While it could be argued that a 2-D approach is adequate for initial construction, the need to see an elevation view of the stack becomes mandatory to achieve correct die spacer selection/definition, die overlap, and clearances. To explore the potential of stacking 8 die in a configuration that meets signal integrity, bondability, routability, etc., requires a method to visualize what the stack looks like as it is being designed.
Some design tools use a post-processed 3-D view. These usually are based on AutoCAD, a mechanical, non-electrically aware system. This post-processed view is useful for verification, but not concept creation and feasibility investigation. A post-processed, 3-D view also is too slow to use for selecting one of many concepts.
Trying to perform such functions in a 2-D plan view mode is difficult, time consuming, and prone to errors. In 2-D, the user must create and manipulate the die (bare die, packaged device, or a mixture) as a set of coincident or offset rectangles. In such a mode, it is difficult to see the position of specific die within the stack. If separation is required between die (spacer), it is hard to tell the difference between a spacer and a die. On top of this, there is a 2-D problem associated with wire bonds. In 2-D, wire bonds look like a plate of tangled spaghetti because the elusive Z-axis element cannot be seen or understood by the designer or the EDA design tool.
Once a stack configuration is constructed, the user would be able to view and interact with a 3-D solid material rendition of the die stack and explore wire bond profile definitions and assignments, as well as design rule check for bondability – especially important when multiple wire tiers are involved. Once a stack concept is selected as viable, it is then placed into the substrate design similar to a package component. As IC packages become more complex and integrate more silicon IP for more device value, while still maintaining a small overall PCB footprint, a designer’s challenge begins to extend into the realm of vertical die stack design. EDA tools must begin to address the Z-axis in 3-D to provide designers and architects with the capabilities they need to stay competitive in today’s rapidly evolving high-tech market.
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KEITH FELTON, product marketing group director, may be contacted at Cadence Design Systems Inc., 720 Billerica Road, Chelmsford, MA 01823; (978) 262-6464; e-mail: [email protected].