I love to sit in airports and imagine what people are like outside of travel. For instance, a fellow just walked by with fur-lined ear flaps on his camo hat and flip flops on his feet. I wonder if he knows the difference between Warren and Jimmy Buffet. I also wonder if I’ll meet up with him in Shanghai as I head out for SEMICON China. This is the travel season when you have to keep multiple schedules on hand. This week’s travel took me to BITS, the burn-in and test socket workshop held in Mesa, Arizona. With new technologies and lots of chip scale packages and wafer scale tests, the test socket market has become a first-class engineering challenge with an increasing global presence. Overall, of the top 25 semiconductor companies, 11 now have U.S. headquarters. Business locations change, as do sockets. Since footprints change for many packages, a socket is required to make the size fit an existing board design. Burn-in and test serve both the OEM and the contract test arena. The functionality increases, pitches get finer, and complexities require more and specialized sockets. Likewise, this expanding workshop had more than 350 attendees and 60 exhibits this year. Chris Lopez, product manager at Antares couldn’t wait to show us the room temperature burn-in rack system (RTBI) that his company had on display. “It’s a rack system where you can run multiple products in the same rack,” he explains. “If you don’t fill an oven, as is normally done, you still don’t waste power. Using only room temperature, you use the chip to help you raise the heat.”
At Sensata Technologies, Hide Furukawa, the U.S. Engineering manager, and Hideyuki Takahashi, the Japanese engineering manager, came up with a system for closing the socket top using a vertical latch system in a burn-in socket. It leaves no pressure scratches, nor does it warp the top of the socket. “IC chips are thinner, faster, and smaller and come in vertical stacks now,” says Furukawa. “Many of my ideas come from customer needs to fit new materials or designs.”
Our next stop was to Freescale in Tempe, Arizona, to visit Karl Johnson, Ph.D., the VP/Senior Fellow, wireless and packaging systems laboratory, and Beth Keser, Ph.D., packaging technology manager, to get a tour of their facility. Johnson delivered the BiTS keynote address the day before covering packaging and assembly issues and some of their unique solutions to meet the latest challenges. At Freescale, Johnson, Keser, and Navjot Chhabara, program manager for redistributed chip package (RCP), talked about their truly disruptive technology. This may change the future of packaging. We went through the operation where RCP packages are fabricated first as 300-mm wafer-style panels that are eventually diced.
“We redistribute power and ground to copper lines and bond pads, getting rid of wirebond interconnect,” says Johnson. Rather than producing 20 packages in a strip, they will produce hundreds in a wafer-style panel.
SEMICON China should bring even more excitement, followed by APEX in Las Vegas. Honestly, sometimes I feel guilty that something so exciting should be called work.
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Gail Flower
Editor-in-Chief