An option for device-stacking applications
By Andrew A. Chambers, Surface Technology Systems
Deep reactive ion etching of silicon (Si DRIE) processes have reached a high level of sophistication over the last 10 years. State-of-the-art DRIE tools are capable of etching deep silicon structures with aspect ratios exceeding 50, selectivity to photoresist ratios exceeding 100:1, and etch depth uniformity better than ±3%. While fundamental process capability has been improved, there have been parallel developments in etch rate and productivity. Silicon etch rates >20 µm/min. are routinely achieved in MEMS manufacturing.
As increasing 2-D device density poses further challenges, there is interest in extending integration into 3-D by device stacking. Typically, wire bonds form interconnections between the die, but this approach restricts interconnects to the periphery of the devices, and limits accessibility when fabricating a large number of wire bonds. An alternative solution is device-stacking using through-wafer vias, and conductive plugs as the interconnections between die. This approach allows for increased interconnect density and avoids large numbers of wire bonds.
Conveniently, DRIE processes used for MEMS fabrication can be adapted to etch through-wafer vias for chip-stacking applications. Both the depth (30 to 200 µm) and the diameter (5 to 70 µm) of vias match the characteristic dimensions of MEMS devices. However, MEMS are typically built on 100- or 150-mm wafers, while IC manufacturers use 200-mm wafers, with much of the industry migrating to 300-mm wafers. Large wafers bring significant cost-per-die benefits, but present the challenge of uniform device processing across the entire wafer. In DRIE processes, issues include etch-depth uniformity and sidewall-profile variation across the wafer diameter.
DRIE Processes
DRIE processes based on the “Bosch process,” or “switched etching process,” provide a means of etching silicon at high rate with excellent anisotropy, while retaining high selectivity over etch masks. The method is made up of sequential repetitions of an etching and polymer-deposition step in a plasma etching system. The polymer-deposition step coats the silicon sidewalls with a protective, passivating film to prevent lateral etching, while the etching step is optimized; first to remove polymer from the base of the etching structures, and then to etch the underlying silicon at high rate. Vital to this process is a high-density plasma capable of providing sufficient etchant species and polymer precursors. Inductively coupled plasma (ICP) etching systems are used, as they offer high-plasma density and operational stability.
The etch rate of a simple ICP system can be increased by applying additional RF power to the plasma and increasing the reactant gas flow. Although these strategies increase the etch rate, additional RF power input increases the available etchant species, but increases the number of ions impinging on the wafer surface. In some cases, the increased ion flux degrades the passivating polymer film, leading to localized damage of the silicon sidewall (Figure 1).
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De-coupled Plasma Sources
To obtain maximum benefit from increased power density in the plasma, such as high etch rate without sidewall damage, the ion flux must be controlled independently of the total power input. This is achieved by employing a “de-coupled” plasma source to generate the reactive species; the plasma is produced within a separate chamber remote from the wafer location, and reactive species are transported to the wafer by diffusion into the reactor vessel. The plasma-source volume is smaller than the chamber volume in a conventional ICP source, and for a given total RF power input, the power density is higher, providing a high degree of dissociation of the process gas. While the source generates a high density of ions, the ion flux to the wafer surface is controlled by an electromagnetic filter at the efflux of the plasma source. By applying dynamic control to the electromagnetic filter, the ion flux at the wafer can be adjusted during the etching process.
Improved Etching Uniformity
A characteristic of small diameter de-coupled plasma sources is the non-uniform ion flux density across the diameter of larger wafers. The system described here is well-adapted for 150-mm wafer processing, but etching of 200-mm wafers presents more serious etch rate and profile uniformity variations across the wafer diameter. This characteristic can be overcome by larger diameter plasma sources, but this approach compromises the plasma density for a given RF power input. Furthermore, the basic non-uniform characteristic of the ion flux from a small diameter source is not properly addressed.
A de-coupled plasma source that provides uniform ion flux across 200-mm wafers while retaining small plasma volume, high RF power density, and high gas dissociation rate of a small-diameter de-coupled source, has recently been developed.* It features a geometrical configuration that distributes high-density plasma over a large diameter, while retaining a small-total plasma volume. Figure 2 compares ion flux characteristics of this source to a small-diameter de-coupled plasma source.
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Dynamic Process Control
Deep, high-aspect-ratio DRIE processes benefit from “parameter ramping;” real-time adjustment of key process parameters throughout the etching process. This technique adjusts the balance between etching and deposition mechanisms by time-varying relevant process parameters; compensating for slower diffusion of etchant species into structures where aspect ratio increases as a function of time.
Silicon etch rate in a “Bosch process” increases when a high pressure etching cycle is used. However, under high-pressure conditions, removal of the passivating polymer film from the trench base is less efficient, and the etch rate is not increased to the maximum. When pressure and wafer bias voltage are varied during each etch step, the process can be simultaneously optimized for maximum etching rate, good uniformity, and maximum selectivity to masking materials. Considering the short cycle times employed in many DRIE processes, such complex process control algorithms require a software package with a large number of user-programmable variables and a tool control system with real-time response.
A DRIE tool control system,** providing the necessary flexibility and response rate, has been developed. The process controller provides both the “parameter ramping” function and the facility to program “boost” and “delay” factors into the individual process steps for all the key process variables. Figure 3 shows examples of the combined “parameter-ramping” and “boost-and-delay” functions.
Optimized Processes for Deep, High-aspect-ratio Through-wafer Vias
Deep, high-aspect-ratio vias are the most challenging DRIE application – through-wafer vias for 3-D chip stacking are a good example. Stacked 3-D chips are built on 200-mm wafers, demanding uniform DRIE processes. Typical etch rate uniformity across a 200-mm wafer (with a 5-mm edge exclusion) is better than ±3%, even when very high silicon etch rates are demanded. High RF power input is applied to maximize the dissociation of the SF6 process gas, and application of the dynamic electromagnetic ion filter ensures that ion flux at the wafer surface is optimized for each step of the process. This avoids the sidewall break-down phenomenon encountered when high RF power was previously used.
Acceptable throughput must be achieved without compromising uniformity, sidewall profile, and selectivity to the mask. To achieve maximum usage of the available etchant species, dynamic process control functions are applied. Process pressure, wafer bias voltage, and electromagnetic filter settings are all profiled throughout each etch step. Currently, 50-µm diameter vias are etched to a depth of 160 µm on 200-mm wafers at an average rate of 15 µm/min.
To avoid the need for excessively thick photoresist masks, the selectivity of the DRIE process is maximized. By using the dynamic process control functions to time-vary the application of high bias voltage to the wafer, the selectivity between photoresist and silicon can be optimized. Selectivity in a typical, high-rate DRIE process can be increased to values approaching 300:1.
Typical through-wafer vias have an aspect ratio high enough to cause problems in judging a single set of process parameters to avoid etch “stalling” before the desired etch depth is reached (the so-called “etch-stop” phenomenon). To counter this problem and avoid “etch-stop,” parameter ramping is used. Process set-ups include ramping down of the process pressure, and ramping up of the wafer bias voltage throughout the etching process, but further parameters may also be ramped depending on the likelihood of etch-stop (e.g., ramping up the etch gas flow, ramping down the deposition gas flow). An optimized process is shown in Figure 4.
 Figure 4. Cross-sectional micrograph of a 50-µm diameter via etched to a depth of 160 µm at a rate of about 13 µm/min. |
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Conclusions
State-of-the-art DRIE systems have evolved from the simple ICP etching systems employed when the Bosch switched process was first offered commercially. Recent advances include etch rate and uniformity improvements on 200-mm wafers by means of an innovative de-coupled plasma source. New, advanced dynamic process control functions allow users to optimize the process set-up to achieve the best possible balance between the conflicting demands of through-wafer via etching processes.
* “Pegasus” DRIE system
References
For a complete list of references, please contact the author.
ANDREW A. CHAMBERS, customer service director, may be contacted at Surface Technology Systems plc, Imperial Park, Newport, Wales, NP10 8UJ; + 44/1633 652 400; E-mail: [email protected].