Those involved in the packaging industry are quite familiar with two key technology drivers: Moore's Law (which dictates that the number of transistors will double in an IC every 24 months), and the increasing need to pack more capability (MIPs, Mbytes, GB/sec) into less space. Without innovations in packaging technology, Moore's Law and the ability to integrate more capability into less space would slow down, if not grind to a halt. The ability to integrate nanotech innovations and systems architecture into the package enables value through differentiation and time-to- market. The future is about integrating nanotech innovations and systems-level trade-offs into new package R&D programs.

Nanotechnology is here! Sub-100-nm gate widths were introduced by Intel in 2000, and Moore's Law continues to be extended by dimensional scaling. The future of Moore's Law will be enhanced by the field of nanotech materials, and innovative applications such as nanowires. Opportunities to use nanotechnology to engineer packaging material properties also are emerging. Some nanomaterials provide free volume control to increase or decrease dielectric constant, while yet other nanomaterials show interactions with light. Depending on size and shape, these materials are resulting in new waveguides, optical fibers and photonic crystals. As this relatively new field is explored, other improved properties are anticipated.

All of these opportunities create new challenges for the packaging industry and academia. Material property control at the molecular level and new metrologies for characterizing morphology and properties are becoming the areas for focus and future innovation. These areas require that we incorporate and embrace new skills in quantum physics, macromolecular science and molecular self-assembly to provide revolutionary materials to enhance package performance. For example, nanoparticles of metals, semiconductors and insulators have unique electronic, thermal and mechanical properties. Expertise is needed to select the right materials, chemically functionalize and integrate them into a package with polymers and interconnects — while exploiting their unique properties.

Similarly, the new maxim for system-in-package (SIP) is about maximizing computing and communication silicon performance, while minimizing the total packaged silicon volume. Computing and communication systems have become more compact and are converging into a single device. Notebook computers now communicate and stream data over wireless RF networks. Cell phones and PDAs provide high levels of computing, communication, and other functions like photography and Web browsing. In 2003, twice as many digital cameras were sold attached to cell phones than digital cameras as stand-alone products. This rise to more compact systems demanding a combination of higher-performance computing, communication and memory silicon is a significant driver for SIP technology.

The past SIP challenge centered on whether two chips could be designed for stacking and assembled in a package through standard wirebond technology. Getting to the more complex integrated stacks of 3 to 6 active die and package-to-package stacks, there are significant challenges to overcome:

• Die thinning to ensure that the thinned wafer functionality is not affected;
• Silicon-to-package integration to ensure stacked silicon will function reliably;
• New materials, assembly equipment and processes required for high volume, high yield and low cost.

Looking forward, it is clear that increasing capability/mm³ through die stacking will continue. Advanced chip-to-package interconnect techniques in development and chip-to-chip interconnect approaches focusing on constructing vias directly through silicon will extend this approach. But the future will be enhanced by the ability to integrate new and dissimilar technologies that currently reside on the system board (RF, analog, digital, MEMS, etc.) seamlessly together into a new breed of system-on-package (SOP) technology. Collaborative R&D between chip designers, silicon and packaging researchers is critical to developing a “system” architecture view. One element that has become evident to me is the boundaries between back-end silicon process, package technology and product design are blurring. To be most effective as SOP technologists, we must develop more broad-based technologists with skills to make effective cost/performance trade-offs in these critical areas.

Advances made by the packaging industry are critical to the continuation of Moore's Law and driving more capability into less space. Our success is measured by delivering the full benefits to the converged computing and communications industry. The packaging industry and academia must continue to invest in the new nanotechnology sciences and advanced SOP architectures to develop a new breed of technologists. The future is here, are you ready?

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NASSER GRAYELI, director of Assembly Technology Development, VP of the Technology Manufacturing Group, may be contacted at Intel Corp., P.O. Box 58119, Santa Clara, CA 95052-8119.